參數(shù)資料
型號(hào)： XR68C192CV-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 4/33頁(yè)
文件大?。?/td> 0K
描述： IC UART FIFI DUAL 44LQFP
標(biāo)準(zhǔn)包裝： 160
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 16 字節(jié)
電源電壓： 2.97 V ~ 5.5 V
帶自動(dòng)流量控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 44-LQFP
供應(yīng)商設(shè)備封裝： 44-LQFP（10x10）
包裝： 托盤
其它名稱： 1016-1644
XR68C192CV-F-ND
XR68C92/192
12
Rev. 1.33
This mode is useful in testing the receiver and transmit-
ter operation of a remote channel. This mode requires
the remote channel receiver to be enabled.
MULTIDROP MODE - Enhanced with Extra A/D Tag
Storage
Users can program the channel to operate in a wake-
up mode for Multidrop applications. In this mode of
operation (set MR1A, MR1B bits 4:3 = 11), the
XR68C92/192, as a master station channel connected
to several slave stations (a maximum of 256 unique
slave stations), transmits an address character fol-
lowed by a block of data characters targeted for one or
more of the slave stations. The channel receivers
within the slave stations are disabled, but they continu-
ously monitor the data stream sent out from the master
station. When the slave stations' receivers detect an
address character, each receiver notifies its respective
CPU by setting receiver ready (-RXRDY) and generat-
ing an interrupt, if programmed to do so. Each slave
station CPU then compares the received address to its
station address and enables its receiver if the ad-
dresses match. Slave stations that are not addressed,
continue monitoring the data stream for the next ad-
dress character. An address character marks the
beginning of a new block of data. After receiving a block
of data, the slave stations CPU may disable the chan-
nel receiver and re-initiate the process.
A transmitted character from the master station con-
sists of a start bit, the programmed number of data bits,
an address/data (A/D) bit tag (replacing the parity bit
used in normal operation), and the programmed num-
ber of stop bits. The A/D tag indicates to the slave
stations channel whether the character should be
interpreted as an address character or a data charac-
ter. The character is interpreted as an address charac-
ter if the A/D tag is set to a '1' or interpreted as a data
character if it is set to a '0'. The polarity of the transmit-
ted A/D tag is selected by programming MR1A, MR1B
bit-2 to a '1' for an address character and to a '0' for data
characters. Users should program the mode register
prior to loading the corresponding data or address
characters into the transmit buffer.
As a slave station, the XR68C92/192 receiver continu-
ously monitors the received data stream regardless of
whether it is enabled or disabled. If the receiver is
disabled, it sets the receiver ready status bit and loads
the character into the FIFO receive holding register
stack provided the received A/D tag is a '1' (address
tag). The received character is discarded if the received
address/data bit is a '0' (data tag). If the receiver is
enabled, all received characters are transferred to the
CPU during read operations. In either case, the data
bits are loaded into the data portion of the FIFO stack
while the address/data bit is loaded into the status
portion of the FIFO stack normally used for parity error
(SRA, SRB bit-5). Framing error, overrun error, and
break-detection operate normally regardless of whether
the receiver is enabled or disabled. The address/data
(A/D) tag takes the place of the parity bit and parity is
neither calculated nor checked for characters in this
mode.
Extra Storage For The A/D Tag: The unique feature of
XR68C92/192 is that the the user need not wait at all in
order to change the A/D tag from address to data
(whereas in the case of SC26C92, a wait of at least 2
bit-times is required before changing the A/D tag). This
allows the user to possibly load the entire polling packet
data to the TX FIFO.
WATCHDOG TIMER
Each of the two receivers (channel A & B) has its own
'watchdog timer' which is separate from and indepen-
dent of the Counter/Timer. The watchdog timer is used
to generate a receive ready time-out interrupt. When it
is enabled, a counter is started everytime a character
is transferred from the receive shift register to the
receive FIFO and times out after 64 bit-times, at which
point it will generate a receive interrupt. This is a useful
feature especially when the incoming data is not a
continous stream of data. For example, if RX trigger
levels are used and the last set of characters is smaller
than the trigger level, a receive time-out interrupt is
generated instead of a regular receive interrupt. The
watchdog timer, however, is not accurate as it uses the
incoming data for its timing. For more accurate timing,
the time-out mode in Counter/Timer should be used
(see below).
COUNTER/TIMER
The 16-bit counter/timer (C/T) can operate in a counter
mode or a timer mode. In either mode, users can
program the C/T input clock source to come from
several sources (see ACR bits 6:4) and program the
C/T output to appear on output port pin OP3 (see
OPCR bits 3:2). The value (pre-load value) stored in
the concatenation of the C/T upper register (CTPU,
address 0x6) and the C/T lower register (CTPL, ad-
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