AC ELECTRICAL CHARACTERISTICS 1, 2, 3 (CONT’D) Test" />
參數(shù)資料
型號(hào)： XR68C681CJTR-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 2/75頁(yè)
文件大?。?/td> 0K
描述： IC UART CMOS DUAL 44PLCC
標(biāo)準(zhǔn)包裝： 500
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 1 字節(jié)，3 字節(jié)
電源電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 44-PLCC（16.59x16.59）
包裝： 帶卷 (TR)
其它名稱： XR68C681CJTR-F-ND
XR68C681
AC ELECTRICAL CHARACTERISTICS 1, 2, 3 (CONT’D)
Test Conditions: TA =0- 70
C, VCC =5.0V +5% unless otherwise specified.
Symbol
Parameter
Min
Typ
Max
Unit
Conditions
Clock Timing (Figure 38)
5
5 $ 5 2! 9(-
: ( <
%
+5
5 $ 5 2! C'&
/5
/
9G
5
9G
Transmitter Timing (Figure 39)
5
5 & 5 2!
:
16
%
5 & 5 #
:
6
%
Receiver Timing (Figure 40)
5
5 ( 5
2! 9(-
=
%
59
5 9$ ( + 5
2! 9(-
%
Notes
1. Parameters are valid over the specified temperature and operating supply ranges. Typical values are 25
C, VCC = 5V and typical
processing parameters.
2. All voltages are referenced to ground (GND). For testing, input signal levels are 0.4V and 2.4V with a transition time of 20ns
maximum. All time measurements are referenced at input voltages of 0.8V and 2.0V as appropriate. See Figure 31.
3. AC test conditions for outputs: CL = 50pF, RL = 2.7k to VCC.
4. Consecutive write operations to the same register require at least three edges of the X1 clock between writes.
5. This specification imposes a 6 MHz maximum 68000 clock frequency if a read or write cycle follows immediately after the previous
read or write cycle. A higher 68000 clock can be used if this is not the case.
6. This specification imposes a lower bound on CS and IACK low, guaranteeing that they will be low for at least one CLK period.
7. This parameter is specified only to insure DTACK is asserted with respect to the rising edge of X1/CLK as shown in the timing dia-
gram, not to guarantee operation of the part. If the specified setup time is violated, DTACK may be asserted as shown or may be
asserted one clock cycle later.
8. The minimum high time must be at least 1.5 times the X1/CLK period and the minimum low time must be at least equal to the X1/CLK
period if either channel’s Receiver is operating in external 1X clock mode.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS1
& ;-
@;
-
/6 6