REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AC ELECTRICAL CHARACTERISTICS Unless otherw" />
參數(shù)資料
型號(hào): XR68M752IL-0B-EB
廠商: Exar Corporation
文件頁(yè)數(shù): 36/54頁(yè)
文件大?。?/td> 0K
描述: EVAL BOARD FOR XR68M752 32QFN
標(biāo)準(zhǔn)包裝: 1
系列: *
XR16M752/XR68M752
41
REV. 1.1.1
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
AC ELECTRICAL CHARACTERISTICS
Unless otherwise noted: TA=-40o to +85oC, Vcc=1.62 - 3.63V, 70 pF load where applicable
SYMBOL
PARAMETER
LIMITS
1.8V ± 10%
MIN
MAX
LIMITS
2.5V ± 10%
MIN
MAX
LIMITS
3.3V ± 10%
MIN
MAX
UNIT
XTAL1
UART Crystal Oscillator
24
MHz
ECLK
External Clock
32
50
64
MHz
TECLK
External Clock Time Period
15
10
7
ns
TAS
Address Setup Time (16 mode)
5
ns
TAH
Address Hold Time (16 mode)
0
ns
TCS
Chip Select Width (16 mode)
60
30
ns
TRD
IOR# Strobe Width (16 mode)
60
30
ns
TDY
Read Cycle Delay (16 mode)
60
30
ns
TRDV
Data Access Time (16 mode)
55
25
ns
TDD
Data Disable Time (16 mode)
0
20
0
20
0
10
ns
TWR
IOW# Strobe Width (16 mode)
60
30
ns
TDY
Write Cycle Delay (16 mode)
60
30
ns
TDS
Data Setup Time (16 mode)
15
10
ns
TDH
Data Hold Time (16 mode)
5
ns
TADS
Address Setup (68 Mode)
5
ns
TADH
Address Hold (68 Mode)
0
ns
TRWS
R/W# Setup to CS# (68 Mode)
5
ns
TRDA
Read Data Access (68 mode)
55
25
ns
TRDH
Read Data Disable (68 mode)
20
10
ns
TWDS
Write Data Setup (68 mode)
15
10
ns
TWDH
Write Data Hold (68 Mode)
5
ns
TRWH
CS# De-asserted to R/W# De-asserted (68
Mode)
5
ns
TCSL
CS# Width (68 Mode)
60
30
ns
TCSD
CS# Cycle Delay (68 Mode)
60
30
ns
TWDO
Delay From IOW# To Output
50
ns
TMOD
Delay To Set Interrupt From MODEM Input
50
ns
TRSI
Delay To Reset Interrupt From IOR#
50
ns
TSSI
Delay From Stop To Set Interrupt
1
Bclk
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