REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO . TABLE
參數(shù)資料
型號(hào): XR68M752IL32TR-F
廠商: Exar Corporation
文件頁(yè)數(shù): 18/54頁(yè)
文件大小: 0K
描述: IC UART FIFO 64B DUAL 32QFN
標(biāo)準(zhǔn)包裝: 3,000
特點(diǎn): *
通道數(shù): 2,DUART
FIFO's: 64 字節(jié)
規(guī)程: RS232,RS422,RS485
電源電壓: 1.62 V ~ 3.63 V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-QFN 裸露焊盤(5x5)
包裝: 帶卷 (TR)
XR16M752/XR68M752
25
REV. 1.1.1
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
.
TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS
A2-A0
REG
NAME
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
COMMENT
16C550 Compatible Registers
0 0 0
RHR
RD
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7]=0
0 0 0
THR
WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0 0 1
IER RD/WR
0/
Modem
Stat. Int.
Enable
RX Line
Stat. Int.
Enable
TX
Empty
Int
Enable
RX Data
Int.
Enable
CTS Int.
Enable
RTS Int.
Enable
Xoff Int.
Enable
Sleep
Mode
Enable
0 1 0
ISR
RD
FIFOs
Enabled
FIFOs
Enabled
0/
INT
Source
Bit-3
INT
Source
Bit-2
INT
Source
Bit-1
INT
Source
Bit-0
INT
Source
Bit-5
INT
Source
Bit-4
0 1 0
FCR
WR
RXFIFO
Trigger
RXFIFO
Trigger
0/
DMA
Mode
Enable
TX FIFO
Reset
RX
FIFO
Reset
FIFOs
Enable
TXFIFO
Trigger
TXFIFO
Trigger
0 1 1
LCR RD/WR Divisor
Enable
Set TX
Break
Set Par-
ity
Even
Parity
Enable
Stop
Bits
Word
Length
Bit-1
Word
Length
Bit-0
1 0 0
MCR RD/WR
0/
Internal
Lopback
Enable
OP2#/
INT Out-
put
Enable
FIFO
Rdy
Enable
(OP1#)
RTS#
Output
Control
DTR#
Output
Control
LCR
≠0xBF
Clock
Pres-
caler
Select
TCR and
TLR
ENable
XonAny
1 0 1
LSR
RD
RX FIFO
Global
Error
THR &
TSR
Empty
THR
Empty
RX
Break
RX
Framing
Error
RX
Parity
Error
RX
Over-
run
Error
RX Data
Ready
1 1 0
MSR
RD
CD#
Input
RI# Input
DSR#
Input
CTS#
Input
Delta
CD#
Delta
RI#
Delta
DSR#
Delta
CTS#
See
1 1 1
SPR RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
See
1 1 0
TCR RD/WR Resume
Bit-3
Resume
Bit-2
Resume
Bit-1
Resume
Bit-0
Halt
Bit-3
Halt
Bit-2
Halt
Bit-1
Halt
Bit-0
See
1 1 1
TLR RD/WR RX Trig
Bit-3
RX Trig
Bit-2
RX Trig
Bit-1
RX Trig
Bit-0
TX Trig
Bit-3
TX Trig
Bit-2
TX Trig
Bit-1
TX Trig
Bit-0
See
1 1 1
FIFO
Rdy
RD
0
RX FIFO
B Status
RX FIFO
A Status
0
TX FIFO
B Status
TX FIFO
A Status
See
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