參數(shù)資料
型號(hào): XR88C92IP
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER
中文描述: 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP40
封裝: PLASTIC, DIP-40
文件頁數(shù): 22/32頁
文件大?。?/td> 186K
代理商: XR88C92IP
XR88C92/192
22
Rev. 1.31
START COUNTER/TIMER REGISTER (STCR) -
Read Only
Reading from this register will start the C/T. Data values
returned should be ignored.
STOP COUNTER/TIMER REGISTER (SPCR) -
Read Only
Reading from this register will stop the C/T. Data values
returned should be ignored.
SET OUTPUT PORT REGISTER (SOPR) -
Write Only
Output ports (OP0-OP7), when used as general pur-
pose outputs, can be asserted (set to low) by writing a
“1” to the corresponding bit in this register. Once an
output is asserted, it can be negated only by issuing a
command through the Reset Output Port Register (see
below).
However, note that SOPR and ROPR cannot be used to
assert and negate outputs that are programmed for
alternate functions (see description under OPCR). For
example, if OP0 is programmed to output -RTSA (see
'Configuring Multi-purpose Outputs), it cannot be con-
trolled by SOPR or ROPR. In that case, commands from
the Command Register should be issued to assert (CRA
bits 7:4 = 0x8) and negate (CRA bits 7:4 = 0x9) OP0.
SOPR Bit 0-7:
0 = No change (same state).
1 = Assert the corresponding output (Set it low).
RESET OUTPUT PORT REGISTER (ROPR) - Write
Only
Each output port bit can be changed to high state by
writing a “1” to each individual bit.
ROPR Bit 0-7:
0 = No change (same state).
1 = Negate the corresponding output (Set it high).
相關(guān)PDF資料
PDF描述
XR88C92IV DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER
XR88C192 DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER
XR88C192CJ DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER
XR88C192CP DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER
XR88C192CV DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER
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