XRA1403
3
REV. 1.0.0
16-BIT SPI GPIO EXPANDER WITH RESET INPUT
PIN DESCRIPTIONS
Pin Description
NAME
PIN#
TYPE
DESCRIPTION
SPI INTERFACE
SO
20
23
O
SPI serial data output.
SCL
19
22
I
SPI bus serial input clock.
IRQ#
22
1
OD
Interrupt output (open-drain, active LOW).
CS#
18
21
I
SPI bus chip select.
SI
23
2
I
SPI serial data input.
RESET#
24
3
I
Reset (active LOW) - A longer than 40 ns LOW pulse on this pin will reset the
internal registers and all GPIOs will be configured as inputs.
GPIOs
P0
P1
P2
P3
P4
P5
P6
P7
1
2
3
4
5
6
7
8
4
5
6
7
8
9
10
11
I/O
General purpose I/Os P0-P7. All GPIOs are configured as inputs upon power-
up or after a reset.
P8
P9
P10
P11
P12
P13
P14
P15
10
11
12
13
14
15
16
17
13
14
15
16
17
18
19
20
I/O
General purpose I/O P8-P15. All GPIOs are configured as inputs upon power-
up or after a reset.
ANCILLARY SIGNALS
VCC
21
24
Pwr
1.65V to 3.6V VCC supply voltage.
GND
9
12
Pwr
Power supply common, ground.
GND
Center
Pad
-
Pwr
The exposed pad at the bottom surface of the package is designed for thermal
performance. Use of a center pad on the PCB is strongly recommended for ther-
mal conductivity as well as to provide mechanical stability of the package on the
PCB. The center pad is recommended to be solder masked defined with open-
ing size less than or equal to the exposed thermal pad on the package bottom to
prevent solder bridging to the outer leads of the device. Thermal vias must be
connected to GND plane as the thermal pad of package is at GND potential.
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
QFN-24 TSSOP-24