REV. 1.0.0 16-BIT SPI GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS 2.17 Input Rising Edge Interrupt Enable Register 1 (REIR" />
參數(shù)資料
型號(hào): XRA1405IG24-0B-EB
廠商: Exar Corporation
文件頁數(shù): 16/16頁
文件大小: 0K
描述: GPIO EXPANDER EVAL BOARD
設(shè)計(jì)資源: XRA140x Eval Board (16-Bit) Schematics
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,GPIO 擴(kuò)展器
嵌入式:
已用 IC / 零件: XRA1405IG24
已供物品:
其它名稱: 1016-1738
XRA1405IG24-OB-EB
XRA1405
9
REV. 1.0.0
16-BIT SPI GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS
2.17
Input Rising Edge Interrupt Enable Register 1 (REIR1) - Read/Write
Writing a ’1’ to these bits will enable the corresponding input to generate an interrupt on the rising edge. See
Table 3 for complete details of the interrupt behavior for various register settings. The MSB of this register
corresponds with P7 and the LSB of this register corresponds with P0.
2.18
Input Rising Edge Interrupt Enable Register 2 (REIR2) - Read/Write
Writing a ’1’ to these bits will enable the corresponding input to generate an interrupt on the rising edge. See
Table 3 for complete details of the interrupt behavior for various register settings. The MSB of this register
corresponds with P15 and the LSB of this register corresponds with P8.
2.19
Input Falling Edge Interrupt Enable Register 1 (FEIR1) - Read/Write
Writing a ’1’ to these bits will enable the corresponding input to generate an interrupt on the falling edge.
Writing a ’1’ to these bits will make that input generate an interrupt on the rising edge only. See Table 3 for
complete details of the interrupt behavior for various register settings. The MSB of this register corresponds
with P7 and the LSB of this register corresponds with P0.
2.20
Input Falling Edge Interrupt Enable Register 2 (FEIR2) - Read/Write
Writing a ’1’ to these bits will enable the corresponding input to generate an interrupt on the falling edge.
Writing a ’1’ to these bits will make that input generate an interrupt on the rising edge only. See Table 3 for
complete details of the interrupt behavior for various register settings. The MSB of this register corresponds
with P15 and the LSB of this register corresponds with P8.
2.21
Input Filter Enable Register 1 (IFR1) - Read/Write
By default, the input filters are enabled (IFR = 0xFF). When the input filters are enabled, any pulse that is
greater than 1075ns will generate an interrupt (if enabled). Pulses that are less than 225ns will be filtered and
will not generate an interrupt. Pulses in between this range may or may not generate an interrupt. Writing a ’0’
to these bits will disable the input filter for the corresponding inputs. With the input filters disabled, any change
on the inputs will generate an interrupt (if enabled). See Table 3 for complete details of the interrupt behavior
for various register settings. The MSB of this register corresponds with P7 and the LSB of this register
corresponds with P0.
2.22
Input Filter Enable Register 2 (IFR2) - Read/Write
By default, the input filters are enabled (IFR = 0xFF). When the input filters are enabled, any pulse that is
greater than 1075ns will generate an interrupt (if enabled). Pulses that are less than 225ns will be filtered and
will not generate an interrupt. Pulses in between this range may or may not generate an interrupt. Writing a ’0’
to these bits will disable the input filter for the corresponding inputs. With the input filters disabled, any change
on the inputs will generate an interrupt (if enabled). See Table 3 for complete details of the interrupt behavior
for various register settings. The MSB of this register corresponds with P15 and the LSB of this register
corresponds with P8.
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