REV. 1.0.0 1.0 FUNCTIONAL DESCRIPTIONS 1.1 SPI bus Interface Th" />
參數(shù)資料
型號(hào): XRA1405IL24-0B-EB
廠商: Exar Corporation
文件頁(yè)數(shù): 11/16頁(yè)
文件大小: 0K
描述: GPIO EXPANDER EVAL BOARD
設(shè)計(jì)資源: XRA140x Eval Board (16-Bit) Schematics
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,GPIO 擴(kuò)展器
嵌入式:
已用 IC / 零件: XRA1405IL24
已供物品:
其它名稱(chēng): 1016-1737
XRA1405IL24-OB-EB
XRA1405
4
16-BIT SPI GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS
REV. 1.0.0
1.0 FUNCTIONAL DESCRIPTIONS
1.1
SPI bus Interface
The SPI interface consists of four lines: serial clock (SCL), chip select (CS#), slave output (SO) and slave input
(SI). The serial clock, slave output and slave input can be as fast as 26 MHz. To access the device in the SPI
mode, the CS# signal is asserted by the SPI master, then the SPI master starts toggling the SCL signal with
the appropriate transaction information. The first bit sent by the SPI master includes whether it is a read or
write transaction and the register being accessed. See Table 1 below.
TABLE 1: SPI COMMAND BYTE FORMAT
BIT
FUNCTION
7
Read/Write#
Logic 1 = Read
Logic 0 = Write
6:1
Command Byte
0
Reserved
FIGURE 3. SPI WRITE
0
A3
A2
A1
A0
X
D7 D6 D5 D4 D3 D2 D1 D0
SCL
SI
FIGURE 4. SPI READ
1
0
0A3
A 2
A1
A0
X
D7
D 6
D5
D 4
D3
D2
D 1
D0
SC L
SI
SO
After the last read or write transaction, the SPI master will set the SCL signal back to its idle state (LOW).
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