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參數(shù)資料
| 型號： | XRD54L10 |
| 廠商： | Exar Corporation |
| 英文描述： | 3V, Low Power, Voltage Output Serial 10-Bit DAC(3V 低功耗 電壓輸出串行10位D/A轉換器) |
| 中文描述： | 3V的，低功耗，電壓輸出，串行10位DAC（3V的低功耗電壓輸出串行10位的D / A轉換器） |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 1012K |
| 代理商： | XRD54L10 |
XRD54L08/L10/L12
7
Rev. 1.30
THEORY OF OPERATION
XRD54L08/L10/L12 Description
The
output,serialdaisy-chainprogrammableDACsoperating
from a single 3V power supply. The DACs are built on a
0.6 micron CMOS process. The features of these DACs
make it well suited for industrial control, low distortion
audio, battery operated devices and cost sensitive
designs that want to minimize pin count on ICs.
XRD54L08/L10/L12
are
micro-power,
voltage
Resistor String DAC
A resistor string architecture converts digital data using a
switch matrix to an analog signal as shown in
Figure 3.
Figure 3. XRD54L08/L10/L12 DAC Architecture
Shift Register
-
+
V
REFIN
V
DD
CS
SCLK
SDIN
Power On
Reset
Switch
Matrix
AGND
V
DD
DOUT
V
OUT
R
R
2
n
The resistor string architecture provides a non-inverted
output voltage (V
OUT
) of the reference input (V
REFIN
) for
singlesupplyoperationwhilemaintainingaconstantinput
resistance.
Unlike inverted R-2R architectures the
reference
input
resistance
independent of code. This greatly simplifies the analog
drivingsourcerequirementsforthereferencevoltageand
minimizes distortion. Similarly input capacitance varies
only approximately 4pF over all codes.
will
remain
constant
Fixed Gain +2 Voltage Output Amplifier
A high open-loop gain operational amplifier buffers the
resistor string with a stable, fixed gain of +2. The voltage
output will settle within 13
s. The output is short circuit
protected and can regulate an output load of 2V into 2k
within 2mV at 25
°
C.
While the reference input will accept a voltage from
rail-to-rail,thelinearinputvoltagerangeisconstrainedby
theoutputswingofthefixed+2closed-loopgainamplifier.
Full scale output swing is achieved with an external
reference of approximately 1/2 V
DD
.
voltage
must
be
positive
XRD54L08/L10/L12 DAC is non-inverting.
The reference
because
the
Serial Daisy-Chainable Digital Interface
ThethreewireserialinterfaceincludesaDOUT toenable
daisy-chaining of several DACs.
count necessary of digital asics or controllers to address
multiple DACS.
The serial interface is designed for
CMOS logic levels.
Timing is shown in
Figure 2
. The
binary coding table (
Table 1)
shows the DAC transfer
function.
This minimizes pin
A power on reset circuit forces the DAC to reset to all“0”s
on power up.
APPLICATION NOTES
Serial Interface
The XRD54L08/L10/L12 family has a three wire serial
interface that is compatible with Microwire
t
, SPI
t
and
QSPI
t
standards. Typical configurations are shown in
Figure 4 and Figure 5
. Maximum serial port clock rate is
limited by the minimum pulse width of t
CH
and t
CL
.
Feedthrough noise from the serial port to the analog
output (V
OUT
) is minimized by lowering the frequency of
the serial port and holding the digital edges to >5ns.
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相關代理商/技術參數(shù) |
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|---|---|
| XRD54L10AID | 制造商:EXAR 制造商全稱:EXAR 功能描述:3V Low Power Voltage Output Serial 8/10/12-Bit DAC Family |
| XRD54L10AID-F | 功能描述:數(shù)模轉換器- DAC RoHS:否 制造商:Texas Instruments 轉換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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