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參數(shù)資料
| 型號(hào)： | XRD6406AIP |
| 廠商： | EXAR CORP |
| 元件分類： | ADC |
| 英文描述： | CMOS 6 MSPS, 10-Bit, High Speed Analog-to-Digital Converter |
| 中文描述： | 1-CH 10-BIT RESISTANCE LADDER ADC, PARALLEL ACCESS, PDIP24 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-24 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 238K |
| 代理商： | XRD6406AIP |
XRD6406
4
Rev. 1.00
ELECTRICAL CHARACTERISTICS TABLE (CONT’D)
Description
Symbol
Min
Typ
Max
Units
Conditions
POWER SUPPLIES
Operating Voltage
(AV
DD
, DV
DD
)
8, 9
Current (AV
DD
+ DV
DD
)
V
DD
I
DD
4.5
5
5.5
17
V
mA
13
25
°
C
Notes:
Testermeasures code transitions by dithering the voltage of the analog input (V
). The difference between the measured and the
ideal code width (V
/1024) is the DNL error (Figure 3.). The INL error is the maximum distance (in LSBs) from the best fit line to
any transition voltage (Figure 4.). Accuracy is a function of the sampling rate (FS).
Guaranteed. Not tested.
Specified values guarantee functionality, but INL & DNL specifications may not be met.
--1 dB bandwidth is a measure of performance of the A/D input stage (S/H + amplifier). Refer to otherparameters for accuracy within
the specified bandwidth.
See V
IN
equivalentcircuit (Figure 8.). Switched capacitoranalog input requires driver with low output resistance.
All inputs have diodes to DV
DD
and DGND. Input DC currents will not exceed specified limits forany input voltage between DGND and
DV
.
Condition to meet aperture delay specifications (t
, t
). Actual rise/fall time can be less stringent with no loss of accuracy.
The AGND & DGND pins are connected through the silicon substrate. Connect togetherat the package and to the analog ground plane.
The AV
DD
& DV
DD
pins should be tied togetherat the package.
2
3
4
5
6
7
8
9
Specifications aresubjectto change withoutnotice
ABSOLUTE MAXIMUM RATINGS (T
A
= +25
°
C unless otherwise noted)
1, 2, 3
AV
DD
to AGND
V
RT
& V
RB
V
IN
. . . . . . . . . . . . . . . . . . . . . . . . . . .
All Inputs
. . . . . . . . . . . . . . . . . . . . . .
All Outputs
. . . . . . . . . . . . . . . . . . . .
+7V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . .
V
DD
+0.5 to GND --0.5V
V
DD
+0.5 to GND --0.5V
V
DD
+0.5 to GND --0.5V
V
DD
+0.5 to GND --0.5V
Storage Temperature
Package Power Dissipation Rating to 75
°
C
PDIP, SOIC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Derates above 75
°
C
. . . . . . . . . . . . . . . . . . . . . . .
Lead Temperature (Soldering 10 seconds)
--65 to +150
°
C
. . . . . . . . . . . . . . . . . . .
1000mW
14mW/
°
C
+300
°
C
. . . . . . .
Notes
1
Stresses above those listed under “Absolute MaximumRatings” may cause permanent damage to the device. This is a
stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
Any input pin which can see a value outside the absolute maximumratings should be protected by Schottky diode clamps
(HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device fromshort
transients outside the supplies of less than 100mA for less than 100
μ
s.
V
DD
refers to AV
DD
and DV
DD
. GND refers to AGND and DGND.
2
3
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