Rev. 3.00 Figure 11. Typical Application Circuitry Internal CIS Rotating Gain and Offset Line-By-Line CIS Line-By-Line Rotating Gain" />
參數(shù)資料
型號(hào)： XRD9827EVAL
廠商： Exar Corporation
文件頁(yè)數(shù)： 14/36頁(yè)
文件大?。?/td> 0K
描述： EVAL BOARD FOR XRD9827
標(biāo)準(zhǔn)包裝： 1
系列： *
XRD9827
21
Rev. 3.00
Figure 11. Typical Application Circuitry Internal CIS Rotating Gain
and Offset Line-By-Line
CIS Line-By-Line Rotating Gain and Offset
(Configuration DB1 = 1, DB0 = 1)
Line-by-line rotating gain and offset minimizes the
amount of write cycles per scan. Pre-loaded values of
gain and offset can be loaded for each color before the
first line is scanned. Each gain and offset is cycled
AVDD
AGND
DGND
VCC (5V - 15V)
DVDD (3V - 5V)
ASIC
DIGITAL
C
I
S
N/C
0
.0
1
u
F
0
.1
u
F
0.1uF
0
.1
u
F
XRD9827
DVDD
1
DB0
2
DB1
3
DB2
4
DB3
5
DB4
6
DB5/SCLK
7
DB6/SDATA
8
DB7/LD
9
DGND
10
ADCCLK
11
CLAMP
12
SYNCH
13
AGND
14
VREF+
15
VDCEXT
16
BLU
17
GRN
18
RED
19
AVDD
20
0
.0
1
u
F
through line-by-line so that the gain and offset do not
have to be loaded in between lines. Below is the typical
application circuit and timing for this configuration.
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