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參數(shù)資料
| 型號： | XRD9853AIV |
| 廠商： | EXAR CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | CCD Image Digitizers with CDS, PGA, and 10-bit A/D |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 MM, 1 MM HEIGHT, TQFP-48 |
| 文件頁數(shù)： | 4/32頁 |
| 文件大?。?/td> | 193K |
| 代理商： | XRD9853AIV |
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XRD9824
4
Rev. 2.10
ELECTRICAL CHARACTERISTICS
Test Conditions: AV
DD
=DV
DD
=5V, ADCCLK=6MHz, 50% Duty Cycle, T
A
=25
°
C unless otherwise specified.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
Power Supplies
AV
DD
DV
DD
I
DD
IDD
PD
Analog Power Supply
Digital I/O Power Supply
Supply Current
Power Down Power Supply Current
ADC Specifications
RES
Resolution
F
s
Maximum Sampling Rate
DNL
Differential Non-Linearity
V
RT
Top Reference Voltage
V
RB
Bottom Reference Voltage
DV
REF
Differential Reference Voltage
(V
RT
- V
RB
)
R
L
Ladder Resistance
PGA & Offset DAC Specifications
3.0
3.0
3.3
3.3
40
5.5
5.5
55
50
V
V
(Note 2)
DV
DD
< AV
DD
V
DD
=5V
V
DD
=5V
mA
μ
A
14
12
-3.0
3.50
Bits
MSPS
LSB
V
V
V
±1.5
AV
DD
/1.3
AV
DD
/10
0.67AV
DD
3.0
3.90
0.6 AV
DD
300
600
780
PGARES
PGAG
MIN
PGAG
MAX
PGAGD
V
BLACK
DACRES
OFF
MIN
OFF
MAX
OFF
MIN
OFF
MAX
OFF
PGA Resolution
Minimum Gain
Maximum Gain
Gain Adjustment Step Size
Black Level Input Range
Offset DAC Resolution
Minimum Offset Adjustment
Maximum Offset Adjustment
Minimum Offset Adjustment
Maximum Offset Adjustment
Offset Adjustment Step Size
6
Bits
V/V
V/V
V/V
mV
Bits
mV
mV
mV
mV
mV
0.950
9.5
1.0
10.0
0.14
1.050
10.50
-100
8
-250
+500
-450
+350
500
DC Configuration
-200
+600
-400
+400
3.14
-150
+700
-350
+450
Mode 111, D5=0 (Note 1)
Mode 111, D5=0
Mode 111, D5=1 (Note 1)
Mode 111, D5=1
Note 1:
The additional ±100 mV of adjustment with respect to the black level input range is needed to compensate
for any additional offset introduced by the XRD9824 Buffer/PGA internally.
It is not recommended to operate the part between 3.6V and 4.4V.
Note 2:
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