Rev. 1.00 CIS Mode Timing -- DC Coupled (CLAMP disabled) ADCCLK tckhw tcklw tckpd tap Pixel N-1 Pixel N tdv Pixel N+1 CIS tdv [7:0]" />
參數(shù)資料
型號: XRD98L23UEVAL
廠商: Exar Corporation
文件頁數(shù): 4/32頁
文件大?。?/td> 0K
描述: EVAL BOARD XRD98L23ACU
標(biāo)準(zhǔn)包裝: 1
系列: *
XRD98L23
12
Rev. 1.00
CIS Mode Timing -- DC Coupled
(CLAMP disabled)
ADCCLK
tckhw
tcklw
tckpd
tap
Pixel N-1
Pixel N
tdv
Pixel N+1
CIS
tdv
[7:0]
N-8
N/A
N-7
N/A
N-6
N/A
N-5
N/A
DB
Figure 6. Timing Diagram for Figure 5
ADCCLK
Events
ADC Sample & PGA Start Tracking next Pixel
Data Out
Invalid Data Out
HI
ADC Track PGA Output
LO
ADC Hold/Convert
Table 1.
Mode 2. AC Coupled
If the CIS signal has a black reference for the video
signal, an external capacitor C
EXT is used.
When
CLAMP (clamp) pin is set high an internal switch allows
one side of the external capacitor to be set to ground.
It then is level shifted to correspond to the bottom ladder
reference voltage of the ADC (Figure 7).
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