Rev. 2.00 4.0 Programmable Gain Amplifier (PGA) The PGA provides gains from 0dB to 36 dB in approxi- mately 0.047 dB steps. The des" />
參數(shù)資料
型號(hào)： XRD98L61EVAL
廠商： Exar Corporation
文件頁(yè)數(shù)： 10/38頁(yè)
文件大?。?/td> 0K
描述： EVAL BOARD FOR XRD98L61AIV
標(biāo)準(zhǔn)包裝： 1
系列： *
XRD98L61
18
Rev. 2.00
4.0 Programmable Gain Amplifier (PGA)
The PGA provides gains from 0dB to 36 dB in approxi-
mately 0.047 dB steps. The desired gain setting is
programmed via the 10 bit gain register in the Serial
Interface.
For gain codes between 0 and 767, the gain can be
calculated by the following equation:
×
=
36
768
]
[
Code
dB
Gain
For gain codes
≥ 768, the gain is fixed at 36 dB. The
gain doubles every 128 codes to simplify DSP algo-
rithms and control.
Gain Code, PGA[9:0]
P
G
A
G
a
in
[d
B
]
0
1
0
2
4
5
1
2
5
6
0
6
7
6
8
12
18
24
30
36
27
9
1
9
2
5
6
8
Figure 7. PGA Gain vs. Gain Code
An example of setting the gain is as follows: If the CCD
input is limited by 800mVpp (CDSVIN) and the ADC full
scale differential input (VID) is 2Vpp, then a minimum
gain is calculated by:
=
CDSV
IN
VID
Gain
20 log
=
0.8
2
20 log
= 8dB
The gain code would be set to 170d for 8dB of PGA
gain.
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