參數(shù)資料
型號(hào): XRK32510
廠商: Exar Corporation
英文描述: 3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS
中文描述: 3.3鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器,10時(shí)鐘輸出
文件頁(yè)數(shù): 3/7頁(yè)
文件大小: 73K
代理商: XRK32510
xr
REV. 1.0.1
XRK32510
3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS
3
PIN DESCRIPTIONS
P
IN
#
P
IN
N
AME
T
YPE
P
IN
D
ESCRIPTION
1
AGND
****
Analog Ground
2
10
14
VDD
VDD
VDD
****
3.3V Power Supply
11
OE
INPUT
Output Enable:
"High" = Normal operation, Clock outputs (QA[0:9]) enabled
"Low" = Clock outputs (QA[0:9]) disabled
12
FB_OUT
OUTPUT
Feedback Output:
When this pin is connected to FB_IN, the propagation delay from
CLK_IN to any of the 10 QA pins will be nearly zero.
13
FB_IN
INPUT
Feedback Input
3
4
5
8
9
15
16
17
20
21
QA0
QA1
QA2
QA3
QA4
QA5
QA6
QA7
QA8
QA9
OUTPUT(S)
Buffered Clock Outputs:
These 10 outputs provide low-skew, low jitter, 50% duty cycle renditions
of CLK_IN
22
VDD
****
3.3V Digital Power Supply
23
AVDD
****
3.3V Analog Supply:
If this pin is connected to ground, the PLL is disabled and will be
bypassed and the CLK_IN signal will be connected directly to the output
buffers of the 10 QA pins.
24
CLK_IN
INPUT
Reference Clock Input
FUNCTIONAL OPERATION
INPUTS
OUTPUTS
PLL
C
ONDITION
OE
AVDD
QA[0:9]
FB_OUT
SOURCE
0
3.3V
0
Driven
PLL
ON
1
3.3V
Driven
Driven
PLL
ON
BUFFER MODE
0
0
0
Driven
CLK_IN
OFF
1
0
Driven
Driven
CLK_IN
OFF
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PDF描述
XRK32510CG 3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRK32510CG 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS
XRK39351 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER
XRK39351_0611 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER
XRK39351CQ 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER
XRK39351IQ 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER