參數(shù)資料
型號: XRK39653_0611
廠商: Exar Corporation
英文描述: 3.3V, 8-OUTPUT ZERO DELAY BUFFER
中文描述: 3.3伏,8輸出零延時緩沖器
文件頁數(shù): 3/9頁
文件大?。?/td> 76K
代理商: XRK39653_0611
xr
XRK39653
REV. 1.0.0
3.3V, 8-OUTPUT ZERO DELAY BUFFER
3
PIN DESCRIPTIONS
N
UMBER
N
AME
T
YPE
D
ESCRIPTION
1
AVDD
Power
Power supply for PLL
2
FB_IN
Input
pull-up
External PLL feedback clock input
3, 4, 5, 6
NC
7
AGND
Power
PLL ground
8
PECL
Input
LVPECL - pos differential reference clock
9
PECL
Input
LVPECL - neg differential reference clock
10
OE
Input
pull-down
Output enable/disable and device reset
11,15, 19,
23, 27,
VDD
Power
Power supply
12, 14, 16,
18, 20, 22,
24, 26
Q[7:0]
Output
Clock outputs
13, 17, 21,
25, 29
GND
Power
Ground
28
QFB
Output
Feedback output for PLL
30
PLL_EN
Input
pull-up
PLL enable/disable select
31
BYPASS
Input
pull-up
PLL and output divider bypass select
32
VCO_SEL
Input
pull-up
VCO divider select
T
ABLE
1: CONTROL INPUT FUNCTION TABLE
Pin Name
0
1
Default
VCO_SEL
System Divide = 4 of VCO output
System Divide = 8 of VCO output
1
PLL_EN
PLL is bypassed and disabled. The PECL
clock reference source drives the outputs
through the divider blocks
PLL enabled. Normal operation. VCO out-
put drives the outputs through the divider
blocks
1
BYPASS
Complete bypass of the PLL and divider
blocks. PECL reference clocks the outputs.
Normal operation. Dividers selected.
1
OE
Outputs enabled
Outputs tri-stated and device reset. VCO
running at minimum frequency
0
相關(guān)PDF資料
PDF描述
XRK39653 3.3V, 8-OUTPUT ZERO DELAY BUFFER
XRK39653CQ 3.3V, 8-OUTPUT ZERO DELAY BUFFER
XRK39653IQ 3.3V, 8-OUTPUT ZERO DELAY BUFFER
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