參數(shù)資料
型號: XRK39910CD-5
廠商: EXAR CORP
元件分類: 時鐘及定時
英文描述: 3.3V LOW SKEW PLL CLOCK DRIVER
中文描述: 39910 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24
封裝: 0.300 INCH, SOIC-24
文件頁數(shù): 4/9頁
文件大?。?/td> 80K
代理商: XRK39910CD-5
XRK39910
4
3.3V LOW SKEW PLL CLOCK DRIVER
REV. 1.0.0
N
OTE
:
(1) These inputs are normally wired to V
DD
, GND, or unconnected. Internal termination resistors bias unconnected
inputs to V
DD
/2. If these inputs are switched, the function and timing of the outputs may be glitched, and the PLL
may require an additional t
LOCK
time before all datasheet limits are achieved.
N
OTE
:
(1) For eight outputs, each loaded with 20pF.
N
OTE
:
(1) Where pulse width implied by D
H
is less than t
PWC
limit, t
PWC
limit applies.
I
3
3-Level Input DC Current (BYPASS, FSEL)
V
IN
= V
DD
HIGH Level
+400
μ
A
V
IN
= V
DD
/2
MID Level
+200
V
IN
= GND
LOW Level
+400
I
PU
Input Pull-Up current (PE)
V
DD
= Max., V
IN
= GND
+100
μ
A
I
PD
Input Pull-Down Current (OE)
V
DD
= Max., V
IN
= V
DD
+100
μ
A
V
OH
Output HIGH Voltage
V
DD
= Min., I
OH
= -12mA
2.4
V
V
OL
Output LOW Voltage
V
DD
= Min., I
OL
= 12mA
0.55
V
T
ABLE
7: POWER SUPPLY CHARACTERISTICS
S
YMBOL
P
ARAMETER
T
EST
C
ONDITIONS(1)
T
YP
.
M
AX
.
U
NIT
I
DDQ
Quiescent Power Supply Current
V
DD
=Max., BYPASS=MID, CLKIN=LOW
V
DD
/PE=LOW, OE=LOW,
All outputs unloaded
8
25
mA
I
TOT
Total Power Supply Current
V
DD
=3.3V, F
REF
=25MHz, C
L
=160pF
(1)
34
mA
V
DD
=3.3V, F
REF
=33MHz, C
L
=160pF
(1)
42
V
DD
=3.3V, F
REF
=66MHz, C
L
=160pF
(1)
76
T
ABLE
8: I
NPUT
T
IMING
R
EQUIREMENTS
S
YMBOL
D
ESCRIPTION(1)
M
IN
.
M
AX
.
U
NIT
t
R
, t
F
Maximum input rise and fall times, 0.8V to 2V
10
ns/V
t
PWC
Input clock pulse, HIGH or LOW
3
ns
D
H
Input duty cycle
10
90
%
Ref
Reference Clock Input
15
85
MHz
T
ABLE
6: DC E
LECTRICAL
C
HARACTERISTICS
OVER
O
PERATING
R
ANGE
S
YMBOL
P
ARAMETER
C
ONDITIONS
M
IN
.
M
AX
.
U
NIT
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