參數(shù)資料
型號: XRK4991
廠商: Exar Corporation
英文描述: 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
中文描述: 3.3高速(85兆赫)可編程相偏時鐘緩沖器
文件頁數(shù): 9/12頁
文件大小: 98K
代理商: XRK4991
xr
REV. 1.0.1
XRK4991
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
9
N
OTES
:
9.
Test measurement levels for the XRK4991 are TTL levels (1.5V to 1.5V). Test conditions assume signal transition
times of 2 ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise
specified.
SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the
same t
U
delay has been selected when all are loaded with 30pF and terminated with 50
to V
CC
/2 (XRK4991).
10.
SWITCHING CHARACTERISTICS
OVER THE 3.3V + 10% OPERATING RANGE
[2,9
]
S
YMBOL
D
ESCRIPTION
XRK4991-2
XRK4991-5
XRK4991-7
U
NIT
M
IN
T
YP
M
AX
M
IN
T
YP
M
AX
M
IN
T
YP
M
AX
t
RPWH
CLKIN Pulse Width HIGH
4
4
4
ns
t
RPWL
CLKIN Pulse Width LOW
4
4
4
ns
t
u
Programmable Skew Unit
See
Table 1
t
SKEWPR
Zero Output Matched-Pair Skew
(Qx[1:0])
[10, 11]
0.05
0.2
0.1
0.25
0.1
0.25
ns
t
SKEW0
Zero Output Skew (All Outputs)
[10, 12]
0.1
0.25
0.25
0.5
0.3
0.75
ns
t
SKEW1
Output Skew (Rise-Rise, Fall-Fall,
Same Class Outputs)
[10, 13]
0.25
0.5
0.6
0.7
0.6
1
ns
t
SKEW2
Output Skew (Rise-Fall, Nominal-
Inverted, Divided-Divided)
[10, 13]
0.3
1
0.5
1
1
1.5
ns
t
SKEW3
Output Skew (Rise-Rise, Fall-Fall,
Different Class Outputs)
[10, 13]
0.25
0.5
0.5
0.7
0.7
1.2
ns
t
SKEW4
Output Skew (Rise-Fall, Nominal-
Divided, Divided-Inverted
[10, 13]
0.5
0.9
0.5
1
1.2
1.7
ns
t
DEV
Device-to-Device Skew
[14, 15]
0.75
1.25
1.65
ns
t
PD
Propagation Delay, CLKIN Rise to
FB_IN Rise
-0.25
0
0.25
-0.5
0
0.5
-0.7
0
0.7
ns
t
ODCV
Output Duty Cycle Variation
[16]
-0.65
0
0.65
-1
0
1
-1.2
0
1.2
ns
t
PWH
Output HIGH Time Deviation from 50%
[17]
2.0
2.5
3
ns
t
PWL
Output LOW Time Deviation from 50%
[17]
1.5
3
3.5
ns
t
ORISE
Output Rise Time
[17, 18]
0.15
1
1.2
0.15
1
1.5
0.15
1.5
2.5
ns
t
OFALL
Output Fall Time
[17, 18]
0.15
1
1.2
0.15
1
1.5
0.15
1.5
2.5
ns
t
LOCK
PLL Lock Time
[19]
0.5
0.5
0.5
ms
t
JR
Cycle-to-Cycle Output
Jitter
RMS
[14]
25
25
25
ps
Peak-to-Peak
[14]
200
200
200
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