參數(shù)資料
型號: XRK4991AIJ-5
廠商: EXAR CORP
元件分類: 時鐘及定時
英文描述: 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
中文描述: 4991 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32
封裝: PLASTIC, LCC-32
文件頁數(shù): 9/13頁
文件大?。?/td> 255K
代理商: XRK4991AIJ-5
xr
REV. P1.0.2
PRELIMINARY
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
XRK4991A
9
N
OTES
:
1.
All timing and jitter tolerances apply for F
NOM
> 25MHz.
Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been
selected when all are loaded with the specified load.
t
SKEWPR
is the skew between a pair of outputs (Qx[1:0]) when all eight outputs are selected for 0t
U
.
t
SKEW0
is the skew between outputs when they are selected for 0t
U
.
2.
3.
4.
T
ABLE
7: S
WITCHING
C
HARACTERISTICS
(3.3
V
+
10% O
PERATING
R
ANGE
)
S
YMBOL
P
ARAMETER
XRK4991A-2
XRK4991A-5
XRK4991A-7
U
NIT
M
IN
T
YP
M
AX
M
IN
T
YP
M
AX
M
IN
T
YP
M
AX
F
NOM
VCO Frequency Range
See PLL Programmable Skew Range and Resolution Table
t
RPWH
CLKIN Pulse Width HIGH
(11)
3
3
3
ns
t
RPWL
CLKIN Pulse Width LOW
(11)
3
3
3
ns
t
u
Programmable Skew Time Unit
See Control Summary Table
t
SKEWPR
Zero Output Matched-Pair Skew (Qx[1:0])
[1,2,3]
0.05
0.2
0.1
0.25
0.1
0.25
ns
t
SKEW0
Zero Output Skew (All Outputs)
[1, 4]
0.1
0.25
0.25
0.5
0.3
0.75
ns
t
SKEW1
Output Skew (Rise-Rise, Fall-Fall, Same
Class Outputs
[1, 6]
0.25
0.5
0.6
0.7
0.6
1
ns
t
SKEW2
Output Skew (Rise-Fall, Divided-Divided)
[1, 6]
0.3
1.2
0.5
1.2
1
1.5
ns
t
SKEW3
Output Skew (Rise-Rise, Fall-Fall, Differ-
ent Class Outputs)
[1, 6]
0.25
0.5
0.5
0.7
0.7
1.2
ns
t
SKEW4
Output Skew
(Rise-Fall, Nominal-Divided,
[1, 2]
0.5
0.9
0.5
1
1.2
1.7
ns
t
DEV
Device-to-Device Skew
[1, 2, 7]
0.75
1.25
1.65
ns
t
PD
CLKIN Input to FB_IN Propagation Delay
[1, 9]
-0.25
0
0.25
-0.5
0
0.5
-0.7
0
0.7
ns
t
ODCV
Output Duty Cycle Variation from 50%
[1]
-1.2
0
1.2
-1.2
0
1.2
-1.2
0
1.2
ns
t
PWH
Output HIGH Time Deviation from 50%
[1,
10]
2
2.5
3
ns
t
PWL
Output LOW Time Deviation from 50%
[1,11]
1.5
3
3.5
ns
t
ORISE
Output Rise Time
[1]
0.15
1
1.2
0.15
1
1.8
0.15
1.5
2.5
ns
t
OFALL
Output Fall Time
[1]
0.15
1
1.2
0.15
1
1.8
0.15
1.5
2.5
ns
t
LOCK
PLL Lock Time
[1,8]
0.5
0.5
0.5
ns
t
JR
Cycle-to-Cycle Output
Jitter
[1]
RMS
25
25
25
ps
Peak-to-Peak
200
200
200
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