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參數(shù)資料
| 型號： | XRK4993CR-2 |
| 廠商： | EXAR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 3.3V PROGRAMMABLE SKEW CLOCK BUFFER |
| 中文描述： | 4993 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 0.150 INCH, QSOP-28 |
| 文件頁數(shù)： | 4/13頁 |
| 文件大?。?/td> | 95K |
| 代理商： | XRK4993CR-2 |
XRK4993
4
3.3V PROGRAMMABLE SKEW CLOCK BUFFER
REV. 1.0.0
SKEW SELECT CONTROL
The skew select control consists of four independent sections. Each bank has two low-skew, high-fanout
drivers (Qx0, Qx1), and two corresponding three-level function select (SELx0, SELx1) inputs. The nine
possible output states for each bank as shown in Table 2 as determined by each bank’s select inputs. All timing
measurements are made with respect to the CLKIN input assuming that the output connected to the FB_IN
input configured for 0 t
U
operation.
N
OTES
:
1.
For all three-level (three-state) inputs, HIGH indicates a connection to V
CC
, LOW indicates a connection to GND,
and MID indicates an open connection. Internal termination circuitry holds an unconnected input to V
CC
/2.
The level to be set on FSEL is determined by the “normal” operating frequency (f
NOM
) of the PLL. Nominal
frequency (f
NOM
) always appears at QA0 and the other outputs when they are operated in their undivided modes
(see Table 2). The frequency appearing at the CLKIN and FB_IN inputs will be f
NOM
when the output connected to
FB_IN is undivided. The frequency of the CLKIN and FB_IN inputs will be f
NOM
/2 or f
NOM
/4 when the part is
configured for a frequency multiplication.
When the FSEL pin is selected HIGH, the CLKIN input must not transition upon power-up until V
CC
has reached
2.8V.
2.
3.
4.
QD[1:0] fixed at zero skew.
BYPASS MODE
BYPASS mode allows the chip to be used in applications where the relative timing between outputs is
maintained but the system clocking is interrupted or at a much lower frequency. An example might be "single-
stepping" the system for diagnostics.
The PLL_BYPASS pin is normally held at Ground (Low). To accommodate low frequency (below the PLL lock
range) or infrequent pulses, the PLL_BYPASS, in conjunction with the FSEL pin (see Table 3) can be used to
by-pass the PLL and generate an output sequence for the CLKIN signal. Relative timing as set by the
SEL(x)1:0 for the various banks will be maintained. The relative timing includes plus and minus n tu and
divide-by (2 or 4) settings. There will be a propagation delay as shown in Table 3. A tu will be approximately
2.5nS with PLL_BYPASS at Mid voltage and 0.4nS in the High state.
T
ABLE
2: P
ROGRAMMABLE
S
KEW
C
ONFIGURATIONS
[1]
F
UNCTION
S
ELECTS
O
UTPUT
F
UNCTIONS
SEL
X
1
SEL
X
0
QA[1:0], QB[1:0]
QC[1:0]
LOW
LOW
-4t
U
Divide by 2
LOW
MID
-3t
U
-6t
U
LOW
HIGH
-2t
U
-4t
U
MID
LOW
-1t
U
-2t
U
MID
MID
0t
U
0t
U
MID
HIGH
+1t
U
+2t
U
HIGH
LOW
+2t
U
+4t
U
HIGH
MID
+3t
U
+6t
U
HIGH
HIGH
+4t
U
Divide by 4
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