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參數(shù)資料
| 型號： | XRK697H73CR |
| 廠商： | EXAR CORP |
| 元件分類： | XO, clock |
| 英文描述： | 1:12 LVCMOS PLL CLOCK GENERATOR |
| 中文描述： | 240 MHz, OTHER CLOCK GENERATOR, PQFP52 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, LQFP-52 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 97K |
| 代理商： | XRK697H73CR |
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
(510) 668-7000
FAX (510) 668-7017
www.exar.com
PRELIMINARY
XRK697H73
1:12 LVCMOS PLL CLOCK GENERATOR
APRIL 2006
REV. P1.0.0
GENERAL DESCRIPTION
The XRK697H73 is a PLL based LVCMOS Clock Generator
targeted for high performance and low skew clock distribu-
tion applications. The XRK697H73 can select between
one of three reference inputs and provides 14 LVCMOS
outputs -12 outputs (3 banks of 4) for clock distribution, 1
for feedback and 1 for synchronization.
The XRK697H73 is a highly flexible device. It has 3 select-
able inputs, (one differential and two single-ended inputs) to
support system clock redundancy. Up to three different
clock frequencys can be generated and outputted on the
three output banks. Switching the internal reference clock
is controlled by the control input, CLK_SEL.
The XRK697H73 uses PLL technology to frequency lock its
outputs to the input reference clock. The divider in the feed-
back path will determine the frequency of the VCO. Each of
the separate output banks can individually divide down the
VCO output frequency. This allows the XRK697H73 to
generate a multitude of different bank frequency ratios and
output-to-input frequency ratios.
The outputs of the XRK697H73 can individually be immobi-
lized, in the low state, by use of the clock stop feature. All
outputs except QC0 and QFB can be immobilized through a
2 pin serial interface. Global output disabling and reset can
be achieved the control input MR/OE.
The XRK697H73 also has a QSYNC output which can be
used for system synchronization purposes. It monitors
Bank A and Bank C outputs and goes low one period of the
faster clock prior to coincident rising edges of Bank A and
Bank C clocks. QSYNC then goes high again when the
coincident rising edges of Bank A and Bank C occur. This
feature is used primarily in applications where Bank A and
Bank C are running at different frequencies, and is
particularly useful when they are running at non-integer
multiples of one another.
The XRK697H73 has an output frequency range of
8.33MHz to 240MHz and an input frequency range of 5MHz
to 120MHz.
FEATURES
Fully Integrated PLL
Selectable Differential PECL or LVCMOS inputs for
reference clock source
14 LVCMOS outputs
■
3 banks with 4 outputs each. Frequencies can
be individually controlled by bank
■
1 dedicated feedback with frequency control
■
1 Sync
VCO Range 200MHz to 480MHz
Output freq. range: 8.33MHz to 240MHz
Max Output Skew of 250ps
Cycle-to-cycle jitter: 150ps (typ)
APPLICATIONS
System Clock generator
Zero Delay Buffer
PRODUCT ORDERING INFORMATION
P
RODUCT
N
UMBER
P
ACKAGE
T
YPE
O
PERATING
T
EMPERATURE
R
ANGE
XRK697H73CR
52-LEAD LQFP
0°C to +70°C
XRK697H73IR
52-LEAD LQFP
-40°C to +85°C
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRK697H73IR | 1:12 LVCMOS PLL CLOCK GENERATOR |
| XRK7933 | INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER |
| XRK7955 | INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER |
| XRK7988 | INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRK697H73IR | 制造商:EXAR 制造商全稱:EXAR 功能描述:1:12 LVCMOS PLL CLOCK GENERATOR |
| XRK7933 | 制造商:EXAR 制造商全稱:EXAR 功能描述:INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER |
| XRK7955 | 制造商:EXAR 制造商全稱:EXAR 功能描述:INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER |
| XRK7988 | 制造商:EXAR 制造商全稱:EXAR 功能描述:INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER |
| XRK79892 | 制造商:EXAR 制造商全稱:EXAR 功能描述:INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER |
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