參數(shù)資料
型號: XRK7955
廠商: EXAR CORP
元件分類: 時鐘及定時
英文描述: INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER
中文描述: 7955 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝: 7 X 7 MM, 1.40 MM HEIGHT, LQFP-32
文件頁數(shù): 3/10頁
文件大?。?/td> 157K
代理商: XRK7955
XRK7955
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER
PRELIMINARY
xr
REV. P1.0.1
3
PIN DESCRIPTIONS
P
IN
N
AME
T
YPE
D
ESCRIPTION
CLK0, CLK0
CLK1, CLK1
LVPECL Input
LVPECL Input
Differential PLL clock reference (CLK0 pulldown, CLK0 pullup)
Differential PLL clock reference (CLK1 pulldown, CLK1 pullup)
Ext_FB, Ext_FB
LVPECL Input
Differential PLL feedback clock (Ext_FB pulldown, Ext_FB pullup)
Qa[1:0], Qa[1:0]
LVPECL Output
Differential 1x output pairs
Qb[2:0], Qb[2:0]
LVPECL Output
Differential 5x output pairs
Inp0bad
LVCMOS Output
Indicates detection of a bad input reference clock 0 with respect to the feed-
back signal. The output is active HIGH and will remain HIGH until the alarm
reset is asserted.
Inp1bad
LVCMOS Output
Indicates detection of a bad input reference clock 1 with respect to the feed-
back signal. The output is active HIGH and will remain HIGH until the alarm
reset is asserted.
Clk_Selected
LVCMOS Output
0 - if clock 0 is selected
1 - if clock 1 is selected
Alarm_Reset
LVCMOS Input
0 - will reset the input bad flags and align Clk_Selected with Sel_Clk. The input
is one-shotted (50K
pullup).
Sel_Clk
LVCMOS Input
0 - selects CLK0
1 - selects CLK1 (40k
pulldown)
Manual_Override
LVCMOS Input
1 - disables internal clock switch circuitry (40K
pulldown).
PLL_En
LVCMOS Input
0 - bypasses selected input reference around the phase-locked loop (50K
pullup).
MR
LVCMOS Input
0 - resets the internal dividers forcing Q outputs LOW. Asynchronous to the
clock (50K
pullup).
VCCA
Power Supply
PLL power supply
VCC
Power Supply
Digital power supply
GNDA
Power Supply
PLL Ground
GND
Power Supply
Digital Ground
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