參數(shù)資料
型號(hào)： XRK7988
廠商： EXAR CORP
元件分類(lèi)： 時(shí)鐘及定時(shí)
英文描述： INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER
中文描述： 7988 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝： 7 X 7 MM, 1.40 MM HEIGHT, LQFP-32
文件頁(yè)數(shù)： 6/10頁(yè)
文件大?。?/td> 155K
代理商： XRK7988
xr
REV. P1.0.1
PRELIMINARY
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER
XRK7988
6
c.
Static phase offset between the selected reference clock and the feedback signal.
d.
Specification holds for a clock switch between two signals no greater than 400ps out of phase. Delta period change
per cycle is averaged over the clock switch excursion. (See Applications Information section for more detail)
e.
Specification holds for a clock switch between two signals no greater than
±π
out of phase. Delta period change per
cycle is averaged over the clock switch excursion.
f.
PECL output termination is 50 ohms to VCC – 2.0V.
g.
V
PP
is the minimum differential input voltage swing required to maintain AC characteristic including SPO, device and
part-to-part skew. Applicable to CLK0, CLK1 and Ext_FB.
h.
V
CMR
is the crosspoint of the differential input signal. Normal operation is obtained when the crosspoint is within the
V
CMR
range and the input swing lies within the V
PP
specification. Violation of V
CMR
or V
PP
impacts the SPO, device
and part-to-part skew. Applicable to CLK0, CLK1 and Ext_FB.
AC C
HARACTERISTICS
(V
CC
= 3.3 + 5%, T
A
= -40
°
C
TO
+85
°
C) (N
OTE
5)
S
YMBOL
P
ARAMETER
M
IN
T
YP
M
AX
U
NIT
C
ONDITION
f
ref
Input Reference Frequency
÷
16 feedback
12.5
25.0
MHz
Locked
f
VCO
PLL VCO Lock Range
200
400
MHz
Qa Output used
for feedback
f
MAX
Output Frequency
Qa[1:0]
Qa[1:0]
12.5
100
25.0
200
MHz
f
refDC
Reference Input Duty Cycle
25
75
%
t
pd
Propagation Delay
CLKn to Ext_FB (SPO)
c
CLKn to Q (Bypass)
-150
150
5
ps
ns
PLL_EN = 1
PLL_EN = 0
V
PP
Differential input voltage (peak-to-peak)
0.25
1.3
V
V
CMR
Differential input crosspoint voltage
V
CC
-1.7
V
CC
-0.3
V
t
skew
Output Skew
Within Qa[1:0] or Qb[2:0]
All outputs
50
80
ps
ps
per/cycle
Rate of change of periods
Qa[1:0]
d
Qb[2:0]
d
Qa[1:0]
e
Qb[2:0]
e
50
25
400
200
ps/cycle
t
pw
Output duty cycle
45
55
%
t
jitter
Cycle-to-cyle jitter, Standard deviation (RMS)
40
ps
@f
ref
=
18.75MHz
t
lock
Maximum PLL lock time
10
ms
t
r
/t
f
Output Rise/Fall time
50
700
ps
相關(guān)PDF資料
PDF描述
XRK79892 INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER
XRK79892IQ INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER
XRK799J93 INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER
XRK799J93IQ INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER
XRS10L120 SERIAL ATA II: 1:2 PORT MULTIPLIER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRK79892 制造商:EXAR 制造商全稱:EXAR 功能描述:INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER
XRK79892IQ 制造商:EXAR 制造商全稱:EXAR 功能描述:INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER
XRK799J93 制造商:EXAR 制造商全稱:EXAR 功能描述:INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER
XRK799J93IQ 制造商:EXAR 制造商全稱:EXAR 功能描述:INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER
XRL100V10 制造商:Xicon Passive Components 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*