參數(shù)資料
型號(hào)： XRT4000
廠商： Exar Corporation
英文描述： Universal Multiprotocol Serial Interface
中文描述： 通用多協(xié)議串行接口
文件頁(yè)數(shù)： 23/46頁(yè)
文件大?。?/td> 396K
代理商： XRT4000
XRT4000
Rev. 1.00
- 23 -
Echoed Clock
The
controllers which have two or three clock pins.
Furthermore, it can handle interfaces (e.g. X.21)
which have only one clock. Information
contained in the Pin Description for the EC* and
2CK/3CK* pins shows how the user can select
the number of available clocks by applying the
appropriate logic levels to these inputs.
XRT4000
can
interface
with
serial
Self-contained DTE Loopback Testing
Equipment having a DTE interface obtains
timing information from another interface (DCE).
RXC and TXC are clocks which are sourced by
the DCE. A DTE device uses them to clock
data in/out of the interface. The SCTE clock is
generated by DTE using TXC or RXC which are
originated in the DCE. In summary, a DTE
equipment is a timing slave.
Occasionally it is beneficial to conduct testing of
a DTE interface without connecting it to its DCE
counterpart. Lack of a synchronization source
will make the standalone testing of DTE
equipment not possible. The XRT4000 has an
on-board oscillator which can be used as a
timing source while the DCE connection is
missing. This feature allows users to conduct
loopback testing on isolated equipment with a
DTE interface.
This mode is invoked if EN_OSC* is set to logic
0. This connects an internally generated clock
signal (32 kHz - 64 kHz) to the RX2D/RX3D
output. A standalone system test may be
performed by combining this feature with the
appropriate loopback mode.
Operational Scenarios
Visualizing features such as clock/data
inversion, echoed clock, and loopbacks, in DTE
and DCE modes makes configuring the
XRT4000 a non-trivial task. A series of 48
system level application diagrams located at the
end of the data sheet called “Scenarios” assist
users in understanding the benefits of these
different features. The internal XRT4000
connections required for a particular scenario
are made through MUX1 and MUX2 that are
shown on the block diagrams given in Figures 2
and 3 respectively. Table 6 contains the signal
routing information versus control input logic
level for MUX1 and Table 7 contains similar
information for MUX2.
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