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參數(shù)資料
| 型號： | XRT56L85 |
| 廠商： | Exar Corporation |
| 英文描述： | Low Power PCM Line Interface |
| 中文描述： | 低功耗的PCM線路接口 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 304K |
| 代理商： | XRT56L85 |
XRT56L85
2
Rev. 2.11
PIN CONFIGURATION
18
1
10
9
2
3
4
5
6
7
15
14
13
12
11
17
16
8
TXV
CC
TPOS
TCLK
TXDATA+
TXGND
TXDATA-
TNEG
RPOS
RNEG
PDC
RXDATA+
RXDATA-
TE
BIAS
TANK BIAS
RXGND
RCLK
RXV
CC
18 Lead PDIP (0.300”)
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
TXV
CC
TPOS
TCLK
TXDATA+
TXGND
TXDATA-
TNEG
RPOS
RNEG
PDC
RXDATA+
RXDATA-
TE
BIAS
TANK BIAS
RXGND
RCLK
RXV
CC
18 Lead SOIC (Jedec, 0.300”)
PIN DESCRIPTION
Pin #
Symbol
Type
Description
1
PDC
Peak Detector Capacitor.
This pin should be connected to a 0.1
μ
F capacitor
Receive Analog Input Positive.
The AMI signal received from the line is applied at this and
the RX DATA(-) pin. Data and clock from the signal applied at these two pins recovered and
output on the RPOS, RNEG, and RCLK pins, respectively.
2
RXDATA+
I
3
RXDATA-
I
Receive Analog Input Negative.
See the description for RX DATA(+).
4
TE
O
LC Tank Excitation Output.
This output connects to one side of the tank circuitry.
5
BIAS
O
Bias.
This pin should be tied to ground through a 0.1
μ
F capacitor.
Tank Reference.
The tank circuitry is biased via this output.
6
TANK BIAS
7
RXGND
Receiver Ground.
To minimize ground interference a separate pin is used to ground the re-
ceiver section.
Recovered Receive Clock.
Recovered clock signal from the AMI signal received at the RX
DATA(+) and RX DATA(-) pins. This signal is output to the terminal equipment.
Receive Supply Voltage.
5V supply voltage for the Receive Section.
8
RCLK
O
9
RXV
CC
RNEG
10
O
Receive Negative Data Output.
A signal at this pin corresponds to the receipt of a negative
pulse on the RX DATA(+)/RX DATA(-) pins. This TTL compatible signal is output to the
terminal equipment.
11
RPOS
O
Receive Positive Data Output.
A signal at this pin corresponds to the receipt of a positive
pulse on the RX DATA(+)/RX DATA pins. This TTL compatible signal is outputed to the
terminal equipment.
12
TNEG
I
Transmit Negative Data Input.
TTL input for a negative polarity pulse (the negative portion
of the AMI pulse train) to be transmitted to the line via the TX DATA(+) and TX DATA pins.
Transmit Negative Data Output.
This pin, along with the TX DATA(+) pin, forms a differential
driver output, this is used to drive AMI data down the line via a transformer. Note: This is an
open-collector output.
13
TXDATA-
O
14
TXGND
Transmit Ground.
15
TXDATA+
O
Transmit Positive Data Output.
Please see description for TX DATA(-).
16
TCLK
I
Transmit Clock.
TPOS and TNEG are sampled on the rising edge of TCLK.
17
TPOS
I
Transmit Positive Data Input.
TTL input for a positive polarity pulse (the positive portion of
the AMI pulse train) to be transmitted to the line via the TX DATA(+) and TX DATA(-) pins.
Transmit Supply Voltage.
5V supply voltage to the transmit section.
18
TXVcc
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XR-T56L85 | 制造商:EXAR 制造商全稱:EXAR 功能描述:Low Power PCM Line Interface |
| XRT56L85D | 制造商:EXAR 制造商全稱:EXAR 功能描述:Low Power PCM Line Interface |
| XR-T56L85D | 制造商:EXAR 制造商全稱:EXAR 功能描述:Low Power PCM Line Interface |
| XRT56L85D-F | 功能描述:外圍驅動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT56L85DTR-F | 功能描述:外圍驅動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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