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參數(shù)資料
| 型號： | XRT6165CDTR-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 14/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL DATA PROCESSOR 24SOIC |
| 產(chǎn)品變化通告： | Packaging Change 15/Jul/2010 |
| 標準包裝： | 1,000 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | E1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 24-SOIC |
| 包裝： | 帶卷 (TR) |
XR-T6165
8
Rev. 2.04
SYSTEM DESCRIPTION
Transmitter
Figure 1 shows the XR-T6165 transmitter section block
diagram. The transmitter converts eight bit bursts or
octets of 2.048Mbps serial data present in a PCM
time-slot to a coded continuous 64kbps data stream.
During operation, data input is controlled by external
clock and time-slot signals, and the 64kbps data output is
timed by an external 256kHz clock. Since the input and
output rates may not be exactly equal because of slight
clock rate dif
ferences, periodic slips can occur
.
Therefore, circuitry is included to delete or repeat octets, if
necessary. Transmitter operation is as follows. Pin
numbers, refer to the DIP package.
PCM data is applied to PCMIN (pin 15), a 2.048MHz local
clock is applied to TX2MHz (pin 16), and a time-slot signal
is applied through the time-slot multiplexer
. This
multiplexer allows the transmitter to be hard wired totwo
time-slot positions. A time-slot signal is applied to
multiplexer inputs TS1T (pin 8) or TS2T (pin 9), and a
time-slot select logic level is applied to TTSEL (pin 12). A
high level at TTSEL selects TS1T while a low level
enables TS2T. The time-slot is an envelope derived
externally from TX2MHz that covers eight clock pulses.
The rising edge of the time-slot signal should be made to
coincide with the falling edge of TX2MHz. Eight bits of
PCM data are clocked into the transmitter input register
on the rising edge of TX2MHz while the selected time-slot
signal is high. The input register data is then transferred
to a storage latch.
Transmission of 64kbps data is controlled by the 256kHz
local clock that is applied to TX256kHz (pin 14). It is not
necessary for this clock to be synchronized with any other
signals that are applied to the transmitter . The output
process begins by transferring data from the storage latch
to the output shift register after transmission of the
previous eight bits of data is complete. Four periods of
TX256kHz are required to encode each data bit. A “l(fā)ogic
0” applied to PCMIN is coded as 0101 while a “l(fā)ogic 1” is
coded as 0011. This data is output on either T+R (pin 10)
or T -R (pin 1 1) according to the AMI (alternate mark
inversion) coding rule. Note that the T+R and T
-R outputs
as well as the corresponding XR-T6164 transmitterinputs
(TX+I/P, TX-I/P) are all active-low. Therefore, a “l(fā)ogic 0”
is coded as a 1010 and a “l(fā)ogic 1” as a 1
100 at the bipolar
transmitter output as specified by CCITT G.703.
Transmission of octet timing is performed by feeding the
seventh and eighth data bits in each word to the same
transmitter output. This function may be inhibited by
setting ALARMIN (pin 13) high to transmit an alarm
condition. Should skew occur between the TX2MHz and
TX256kHz clocks signals, or during an adjustment of the
timing of the time-slot signal, circuitry is included to delete
or repeat complete words of data. This could happen, for
example, when changing from one time-slot position to
another. A byte repetition or insertion occurs once if no
new PCM data is received. A byte repetition just occurs
once. If no new PCM data is received, the T+R and T-R
outputs stay high. A byte deletion occurs when the
transmitter receives a new byte of data before the
previous byte is transferred from the storage latch to the
output register. Under this condition, the stored data is
overwritten.
Receiver
Figure 2 shows the block diagram of the XR-T6165
receiver section. The receiver converts coded
continuous 64kbps data to eight bit bursts of 2.048Mbps
serial data suitable for insertion in a PCM time-slot.
During operation, data input is timed by a clock that is
extracted from the input signal, while output is controlled
by external locally supplied clock and time-slot signals.
Since the data input and output rates may not be exactly
equal, circuitry is included to delete or repeat eight bit data
blocks, if necessary. Receiver operation is as follows.
A line interface chip such as the receive section of the
XR-T6164 converts the encoded bipolar 64kbps signal to
dual-rail active-low logic levels. These signals are
applied to the XR-T6165 receiver S+R (pin 1) and S-R
(pin 2) inputs. A 128kHz clock, which is derived from the
received signal, is used to decode this data, and then to
clock it into one of two storage registers. T wo registers
are used so that one may be receiving continuous data at
64kbps while the other is sending eight bit bursts at a
2.048Mbps rate to PCMOUT (pin 21) while the receiver
time-slot signal is high. The time-slot is an envelope
derived externally from RX2MHz that covers eight clock
pulses. The rising edge of the time-slot signal should be
made to coincide with the rising edge of RX2MHz. Eight
bits of PCM data are clocked out of the receiver register
on the rising edge of RX2MHz while the time-slot signal is
high. A two input multiplexer at the time-slot input allows
the receiver to be hard wired to two time-slot positions.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XR-T6165CP | 制造商:EXAR 制造商全稱:EXAR 功能描述:Codirectional Digital Data Processor |
| XR-T6165ID | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Time-Slot Assigner |
| XRT6165ID-F | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT6165IDTR-F | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XR-T6165IP | 制造商:EXAR 制造商全稱:EXAR 功能描述:Codirectional Digital Data Processor |
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