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參數(shù)資料
| 型號： | XRT7295AE |
| 廠商： | Exar Corporation |
| 英文描述： | E3 (34.368Mbps) Integrated line Receiver |
| 中文描述： | E3展（34.368Mbps）綜合線路接收器 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大小： | 861K |
| 代理商： | XRT7295AE |
XRT7295AE
9
Rev. 2.0.0
False-Lock Immunity
False-lock is defined as the condition where a PLL
recovered clock obtains stable phase-lock at a fre-
quency not equal to the incoming data rate. The
XRT7295AE uses a combination frequency/phase-
lock architecture to prevent false-lock. An on-chip
frequency comparator continuously compares the
EXCLK reference to the PLL clock. If the frequency
difference between the EXCLK and PLL clock exceeds
approximately +/-0.5% of EXCLK, correction circuitry
acts to force the reacquisition of the proper frequency
and phase.
Acquisition Time
If a valid input signal is assumed to be already present
at RIN, the maximum time between the application of
device power and error-free operation is 20ms. If power
has already been applied, the interval between the
application of valid data and error-free operation is 4ns.
Loss-of-Lock Indication
As previously stated, the PLL acquisition aid circuitry
monitors the PLL clock frequency relative to the
EXCLK frequency.
The acquisition circuit also monitors the resumed data
to detect possible phase-lock which is 180° out of a
normal phase alignment. The RLOL alarm is activated
if either or both of the following conditions exist:
- The difference between the PLL clock and the
EXCLK frequency exceeds approximately +/-
0.5%.
- The retimed data is 180° out of a normal phase
alignment.
A high RLOL output indicates that the acquisition
circuit is working to bring the PLL into proper frequency
lock. RLOL remains high until frequency lock has
occurred; however, the minimum RLOL pulse width is
32 clock cycles.
Loss-of-Signal Detection
Figure 1 shows that analog and digital methods of loss-
of-signal (LOS) detection are combined to create the
RLOS alarm output. RLOS is set if either the analog or
digital detection circuitry indicates LOS has occurred.
Analog Detection
The analog LOS detector monitors the peak input
signal amplitude. RLOS makes a high-to-low transition
(input signal regained) when the input signal amplitude
exceeds the loss-of-signal threshold defined in Table
4. The RLOS low-to-high transition (input signal loss)
occurs at a level typically 1.0dB below the high-to-low
transition level. The hysteresis prevents RLOS chat-
tering. Once set, the RLOS alarm remains high for at
least 32 clock cycles, allowing for system detection of
a LOS condition without the use of an external alarm
latch.
To allow for varying levels of noise and crosstalk in
different applications, three loss-of-signal threshold
settings are available using the LOSTHR pin. Setting
LOSTHR = V
DD
provides the lowest loss-of-signal
threshold; LOSTHR = V
DD
/2 (can be produced using
two 50k
+/-10% resistor as a voltage divider between
V
DD
D and GNDD) provides an intermediate threshold.
LOSTHR = GND provides the highest threshold. The
LOSTHR pin must be set to its desired value at power
up and must not be changed during operation.
Data
Rate
Threshold
MIN
REQB LOSTHR
Max
Unit
0
0
60
220
mV pk
E3
V
DD
/2
40
145
mV pk
34.368
V
DD
25
90
mV pk
Mbps
1
0
45
175
mV pk
V
DD
/2
30
115
mV pk
V
DD
20
70
mV pk
Notes:
1
The RLOS alarm is an indication of the presence of an
input signal, not a bit error rate indication. Table 1
gives the minimum input amplitude needed for error-
free operation (BER<1E
-9
). Independent of the RLOS
state, the device will attempt to recover correct timing
and data.
2
The RLOS low-to-high transition typically occurs 1dB
below the high-to-low transition.
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| XRT7295AEIW | E3 (34.368Mbps) Integrated line Receiver |
| XRT7295AT | DS3/Sonet STS-1 Integrated Line Receiver |
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| XRT7295 | () |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XRT7295AE_03 | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3 (34.368Mbps) Integrated line Receiver |
| XRT7295AEIW | 功能描述:外圍驅動器與原件 - PCI E3 Line Receiver RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT7295AEIW-F | 功能描述:外圍驅動器與原件 - PCI E3 Line Receiver RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT7295AEIWTR | 功能描述:外圍驅動器與原件 - PCI E3 Line Receiver RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT7295AEIWTR-F | 功能描述:外圍驅動器與原件 - PCI E3 Line Receiver RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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