參數(shù)資料
型號(hào): XRT7296
廠商: Exar Corporation
英文描述: INTEGRATED LINE TRANSMITTER
中文描述: 集成線路變送器
文件頁(yè)數(shù): 5/16頁(yè)
文件大?。?/td> 443K
代理商: XRT7296
XRT7296
&
ELECTRICAL CHARACTERISTICS
(See Figure 8 )
Test Conditions: V
DD
= 5V
±
5%, T
A
= -40 C to +85 C, unless otherwise specified. All timing characteristics
are measured with 10pF loading.
Symbol
Parameter
Min.
Typ.
Max.
Units
AC Electrical Characteristics
# +/; ,- -/+ ' *(
&
&
&&
F
# +/; ,- -/+ '(
"
&
&
F
# +/; 'F %F(
$
# +/; $++ 'F %F(
07 # $++
:=
07 # $++ :+
&
I
075 # 0 +-
)
# +/; ,- -/+
&
&
&&
F
# +/; 'F %F(
$
# +/; $++ 'F %F(
07 # $++
:=
07 # $++ :+
&
#= +/; 'F %F(
$
#= +/; $++ 'F %F(
I
0=7579 #= 0
+-
DC Electrical Characteristics
<
<
, +- <+
"&
&
&&
<
, +- ,
<
, 2 <+
&
<
<
:
, :1 <+
<
J "
<
<
<
=
=, , 2 <+
=
K*
57
<
<
=:
=, , :1 <+
=
K
<
* &
<
<
, ; ,
±
0 %) ' ,K<(
*&
*&
, //
$
//
$
Notes
:
1
Whentheencoderisenabled,ahandlingdelayoffourandahalfTCLKclockcyclesforB3ZSandfiveandhalfclockcyclesfor HDB3
always exists between TPDATA/TNDATA and TTIP/TRING. The handling delay is reduced to two clock cycles when the encoder
is disabled.
2
When the decoder is enabled, a handling delay of six and a half RCLK clock cycles will always exist between RPDATA/RNDATA
and RPOS/RNEG/RNRZ. The handling delay is reduced to one and half RCLK clock cycles when the decoder is disabled.
3
Supply current is measured with transmitter sending all ones AMI signal and with Transmit Level (TXLEV) set to high.
4
All inputs except pin 19, 20 and pin 26.
Specifications are subject to change without notice
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