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參數(shù)資料
| 型號： | XRT7300IV |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 3/55頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E3/DS3/STS-1 SGL 44TQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LQFP |
| 供應(yīng)商設(shè)備封裝： | 44-TQFP（10x10） |
| 包裝： | 托盤 |
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XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.2
7
27
EXCLK
I
External Reference Clock Input:
Apply a 34.368MHz clock signal for E3 applications, a 44.736 MHz clock signal
for DS3 applications or a 51.84 MHz clock signal for SONET STS-1 applications.
28
GND
****
Receiver Digital Ground
29
VDD
****
Receiver Digital VDD
30
LCV/(RCLK2)
O
Line Code Violation Indicator/Receive Clock Output pin 2:
The function of this pin depends upon whether the XRT7300 is operating in the
HOST Mode, the Hardware Mode or User selection.
HOST Mode - Line Code Violation Indicator Output:
If the XRT7300 is configured to operate in the HOST Mode, then this pin func-
tions as the LCV output pin by default. However, by using the on-chip Command
Registers, this pin can be configured to function as the second Receive Clock
signal output pin (RCLK2).
Hardware Mode - Receive Clock Output pin 2:
This output pin is the Recovered Clock signal from the incoming line signal. The
receive section of the XRT7300 outputs data via the RPOS and RNEG output
pins on the rising edge of this clock signal.
NOTE: If the XRT7300 is operating in the HOST Mode and this pin is configured
to function as the additional Receive Clock signal output pin, then the XRT7300
can be configured to update the data on the RPOS and RNEG output pins on the
falling edge of this clock signal.
31
RCLK1
O
Receive Clock Output pin 1:
This output pin is the Recovered Clock signal from the incoming line signal. The
receive section of the XRT7300 outputs data via the RPOS and RNEG output
pins on the rising edge of this clock signal.
NOTE: If the XRT7300 device is operating in the “Host” Mode, then the user can
configure the device to update the data on the RPOS and RNEG output pins on
the falling edge of this clock signal.
32
RNEG
O
Receive Negative Pulse Output:
This output pin pulses “High” whenever the XRT7300 has received a Negative
Polarity pulse in the incoming line signal at the RTIP/RRING inputs.
NOTE: If the B3ZS/HDB3 Decoder is enabled, then the zero suppression pat-
terns in the incoming line signal (such as: "00V", "000V", "B0V", "B00V") is not
reflected at this output.
33
RPOS
O
Receive Positive Pulse Output:
This output pin pulses “High” whenever the XRT7300 has received a Positive
Polarity pulse in the incoming line signal at the RTIP/RRING inputs.
NOTE: If the B3ZS/HDB3 Decoder is enabled, then the zero suppression pat-
terns in the incoming line signal (such as: "00V", "000V", "B0V", "B00V") is not
reflected at this output.
34
ICT
I
In-Circuit Test Input:
Setting this pin “Low” causes all digital and analog outputs to go into a high-
impedance state to allow for in-circuit testing. This pin is internally pulled “High”.
PIN DESCRIPTION
PIN #SYMBOL
TYPE
DESCRIPTION
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參數(shù)描述 |
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| XRT7300IV-F | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT7300IVTR | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT7300IVTR-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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| XRT73L00 | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT |
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