參數(shù)資料
型號: XRT73L02MIV-F
廠商: Exar Corporation
文件頁數(shù): 39/46頁
文件大?。?/td> 0K
描述: IC LIU E3/DS3/STS-1 2CH 100TQFP
標(biāo)準(zhǔn)包裝: 90
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 2/2
規(guī)程: DS3,E3,STS-1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
包裝: 托盤
XRT73L02M
xr
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.0
42
During the remote loop back mode, if the jitter attenuator is selected in the transmit path, the receive data after
the Clock and Data Recovery Block is looped back to the transmit path and passed through the jitter attenuator
using RxClk as the transmit timing.
NOTE: Input signals on TxClk, TPOS and TNEG are ignored during Remote loop back.
8.3
TRANSMIT ALL ONES (TAOS):
Transmit All Ones (TAOS) can be set either in Hardware mode by pulling the TAOS_n pins “High” or in Host
mode by setting the TAOS_n control bits to “1” in the Channel control registers. When the TAOS is set, the
Transmit Section generates and transmits a continuous AMI all “1’s” pattern on TTIP_n and TRING_n pins. The
frequency of this “1’s” pattern is determined by TxClk_n.TAOS data path is shown in Figure 29.
FIGURE 27. REMOTE LOOPBACK
FIGURE 28. TRANSMIT ALL ONES (TAOS)
TRING
TTIP
RRING
RTIP
RPOS
RNEG
RCLK
TNDATA
TCLK
TPDATA
HDB3/B3ZS
ENCODER
HDB3/B3ZS
DECODER
JI
TTE
R
2
AT
T
E
NUAT
O
R
JI
TTE
R
2
AT
T
E
NUAT
O
R
TIMING
CONTROL
DATA &
CLOCK
RECOVERY
1 if enabled
2 if enabled and selected in either Receive or
Transmit path
Tx
Rx
1
TRING
TTIP
RRING
RTIP
RPOS
RNEG
RCLK
TNDATA
TCLK
TPDATA
HDB3/B3ZS
ENCODER
HDB3/B3ZS
DECODER
JITTER
2
ATTENUATOR
JITTER
2
ATTENUATOR
TIMING
CONTROL
DATA &
CLOCK
RECOVERY
1 if enabled
2 if enabled and selected in either Receive or
Transmit path
Tx
Rx
TAOS
Transmit All 1'
1
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