PIN DESCRIPTIONS (BY FUNCTION
參數(shù)資料
型號(hào): XRT73L06IB
廠商: Exar Corporation
文件頁數(shù): 61/63頁
文件大小: 0K
描述: IC LIU E3/DS3/STS-1 6CH 217BGA
標(biāo)準(zhǔn)包裝: 60
類型: 線路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 6/6
規(guī)程: DS3,E3,STS-1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 217-BBGA
供應(yīng)商設(shè)備封裝: 217-BGA(23x23)
包裝: 托盤
XRT73L06
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
4
PIN DESCRIPTIONS (BY FUNCTION)
TRANSMIT INTERFACE
LEAD #SIGNAL NAME
TYPE
DESCRIPTION
T15
R16
R15
N14
P14
P13
TxON_0
TxON_1
TxON_2
TxON_3
TxON_4
TxON_5
I
Transmitter ON Input - Channel 0:
Transmitter ON Input - Channel 1:
Transmitter ON Input - Channel 2:
Transmitter ON Input - Channel 3:
Transmitter ON Input - Channel 4:
Transmitter ON Input - Channel 5:
These pins are active only when the corresponding TxON bits are set.
Table below shows the status of the transmitter based on theTxON bit and TxON
pin settings.
NOTES:
1. These pins will be active and can control the TTIP and TRING outputs only
when the TxON_n bits in the channel register are set .
2. When Transmitters are turned off the TTIP and TRING outputs are Tri-
stated.
3. These pins are internally pulled up.
E3
M3
F15
P16
G3
H15
TxCLK_0
TxCLK_1
TxCLK_2
TxCLK_3
TxCLK_4
TxCLK_5
I
Transmit Clock Input for TPOS and TNEG - Channel 0:
Transmit Clock Input for TPOS and TNEG - Channel 1:
Transmit Clock Input for TPOS and TNEG - Channel 2:
Transmit Clock Input for TPOS and TNEG - Channel 3:
Transmit Clock Input for TPOS and TNEG - Channel 4:
Transmit Clock Input for TPOS and TNEG - Channel 5:
The frequency accuracy of this input clock must be of nominal bit rate ± 20 ppm.
The duty cycle can be 30%-70%.
By default, input data is sampled on the falling edge of TxCLK.
Bit
0
Transmitter Status
OFF
Pin
0
1
OFF
ON
0
1
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