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參數(shù)資料
| 型號： | XRT73LC04AIV |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144 |
| 文件頁數(shù)： | 11/64頁 |
| 文件大小： | 360K |
| 代理商： | XRT73LC04AIV |
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XRT73LC04A
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
7
80
88
101
93
RTIP_0
RTIP_1
RTIP_2
RTIP_3
I
Receive TIP Input - Channel (n):
This input pin along with RRing_(n) is used to receive the bipolar line sig-
nal from the Remote DS3/E3/STS-1 Terminal.
82
90
99
91
REQEN_0
REQEN_1
REQEN_2
REQEN_3
I
Receive Equalization Enable Input - Channel (n):
Setting this input pin "High" enables the Internal Receive Equalizer
within Channel (n). Setting this pin "Low" disables the Internal Receive
Equalizer. The guidelines for enabling and disabling the Receive Equal-
izer are described in Section 3.2.
N
OTE
:
This pin is ignored and should be tied to GND if the XRT73LC04A
is going to be operating in the HOST Mode, (internally pulled-down).
110
RxClkINV
I
Invert RxClk_(n) Output - Select:
The function of this pin depends upon the mode of operation.
Hardware Mode - Invert RxClk Output Select:
Setting this input pin "High" configures the Receive Section of all Chan-
nels to invert their RxClk_(n) clock output signals.
Setting this pin "Low" configures Channel(n) to output the recovered
data via the RPOS_(n) and RNEG_(n) output pins on the rising edge of
RxClk_(n).
Setting this input pin "High" configures Channel (n) to output the recov-
ered data via the RPOS_(n) and RNEG_(n) output pins on the falling
edge of RxClk_(n).
N
OTE
:
This pin is internally pulled “High”.
RECEIVE INTERFACE
P
IN
#
N
AME
T
YPE
D
ESCRIPTION
CLOCK INTERFACE
P
IN
#
N
AME
T
YPE
D
ESCRIPTION
66
57
115
123
EXClk_0
EXClk_1
EXClk_2
EXClk_3
I
External Reference Clock Input - Channel (n):
Apply a 34.368 MHz clock signal for E3 applications, a 44.736 MHz
clock signal for DS3 applications or a 51.84 MHz clock signal for SONET
STS-1 applications.
The Channel (n) Clock Recovery PLL uses this signal as a Reference
Signal for Declaring and Clearing the Receive Loss of Lock Alarm. The
Clock recovery PLL also generates the exact clock for the LIU.
It is permissible to use the same clock that drives the TxClk_(n) input
pin.
It is permissible to operate the four Channels at different data rates.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT73R06 | SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73R06IB | SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73R12 | TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73R12IB | TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT74L73 | 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT73LC04AIV-F | 功能描述:外圍驅(qū)動器與原件 - PCI 4-Ch DS3, E3, STS-1 RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT73R06 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73R06ES | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT73R06IB | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT73R06IB-F | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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