參數(shù)資料
型號： XRT73R12
廠商： Exar Corporation
英文描述： TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
中文描述： 第十二章通道E3/DS3/STS-1線路接口單元
文件頁數(shù)： 4/87頁
文件大?。?/td> 436K
代理商： XRT73R12
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. P1.0.3
PRELIMINARY
II
F
IGURE
17. D
UAL
-R
AIL
D
ATA
F
ORMAT
(
ENCODER
AND
DECODER
ARE
DISABLED
).................................................................................... 29
F
IGURE
18. B3ZS E
NCODING
F
ORMAT
................................................................................................................................................. 29
4.4 TRANSMIT PULSE SHAPER ......................................................................................................................... 30
F
IGURE
20. T
RANSMIT
P
ULSE
S
HAPE
T
EST
C
IRCUIT
.............................................................................................................................. 30
4.4.1 GUIDELINES FOR USING TRANSMIT BUILD OUT CIRCUIT .................................................................................. 30
F
IGURE
19. HDB3 E
NCODING
F
ORMAT
................................................................................................................................................. 30
4.5 E3 LINE SIDE PARAMETERS ........................................................................................................................ 31
F
IGURE
21. P
ULSE
M
ASK
FOR
E3 (34.368
MBITS
/
S
)
INTERFACE
AS
PER
ITU
-
T
G.703 ............................................................................. 31
T
ABLE
4: E3 T
RANSMITTER
LINE
SIDE
OUTPUT
AND
RECEIVER
LINE
SIDE
INPUT
SPECIFICATIONS
.............................................................. 32
F
IGURE
22. B
ELLCORE
GR-253 CORE T
RANSMIT
O
UTPUT
P
ULSE
T
EMPLATE
FOR
SONET STS-1 A
PPLICATIONS
................................. 33
T
ABLE
5: STS-1 P
ULSE
M
ASK
E
QUATIONS
........................................................................................................................................... 33
T
ABLE
6: STS-1 T
RANSMITTER
L
INE
S
IDE
O
UTPUT
AND
R
ECEIVER
L
INE
S
IDE
I
NPUT
S
PECIFICATIONS
(GR-253)..................................... 34
F
IGURE
23. T
RANSMIT
O
UPUT
P
ULSE
T
EMPLATE
FOR
DS3
AS
PER
B
ELLCORE
GR-499 ......................................................................... 34
T
ABLE
8: DS3 T
RANSMITTER
L
INE
S
IDE
O
UTPUT
AND
R
ECEIVER
L
INE
S
IDE
I
NPUT
S
PECIFICATIONS
(GR-499)........................................ 35
T
ABLE
7: DS3 P
ULSE
M
ASK
E
QUATIONS
............................................................................................................................................... 35
4.6 TRANSMIT DRIVE MONITOR ........................................................................................................................ 36
4.7 TRANSMITTER SECTION ON/OFF ............................................................................................................... 36
F
IGURE
24. T
RANSMIT
D
RIVER
M
ONITOR
SET
-
UP
................................................................................................................................... 36
5.0 JITTER ..................................................................................................................................................37
5.1 JITTER TOLERANCE ..................................................................................................................................... 37
5.1.1 DS3/STS-1 JITTER TOLERANCE REQUIREMENTS................................................................................................ 37
F
IGURE
25. J
ITTER
T
OLERANCE
M
EASUREMENTS
.................................................................................................................................. 37
5.1.2 E3 JITTER TOLERANCE REQUIREMENTS.............................................................................................................. 38
F
IGURE
26. I
NPUT
J
ITTER
T
OLERANCE
F
OR
DS3/STS-1 ...................................................................................................................... 38
F
IGURE
27. I
NPUT
J
ITTER
T
OLERANCE
FOR
E3..................................................................................................................................... 38
5.2 JITTER TRANSFER ........................................................................................................................................ 39
T
ABLE
9: J
ITTER
A
MPLITUDE
VERSUS
M
ODULATION
F
REQUENCY
(J
ITTER
T
OLERANCE
)........................................................................... 39
T
ABLE
10: J
ITTER
T
RANSFER
S
PECIFICATION
/R
EFERENCES
................................................................................................................... 39
T
ABLE
11: J
ITTER
T
RANSFER
P
ASS
M
ASKS
........................................................................................................................................... 39
5.2.1 JITTER GENERATION................................................................................................................................................ 40
F
IGURE
28. J
ITTER
T
RANSFER
R
EQUIREMENTS
..................................................................................................................................... 40
6.0 DIAGNOSTIC FEATURES ...................................................................................................................41
6.1 PRBS GENERATOR AND DETECTOR ......................................................................................................... 41
F
IGURE
29. PRBS MODE ................................................................................................................................................................... 41
6.2 LOOPBACKS .................................................................................................................................................. 42
6.2.1 ANALOG LOOPBACK................................................................................................................................................ 42
F
IGURE
30. A
NALOG
L
OOPBACK
........................................................................................................................................................... 42
6.2.2 DIGITAL LOOPBACK................................................................................................................................................. 43
6.2.3 REMOTE LOOPBACK................................................................................................................................................ 43
F
IGURE
31. D
IGITAL
L
OOPBACK
............................................................................................................................................................ 43
F
IGURE
32. R
EMOTE
L
OOPBACK
........................................................................................................................................................... 43
6.3 TRANSMIT ALL ONES (TAOS) ...................................................................................................................... 44
F
IGURE
33. T
RANSMIT
A
LL
O
NES
(TAOS) ............................................................................................................................................ 44
7.0 MICROPROCESSOR INTERFACE BLOCK ........................................................................................45
T
ABLE
12: S
ELECTING
THE
M
ICROPROCESSOR
I
NTERFACE
M
ODE
.......................................................................................................... 45
F
IGURE
34. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
M
ICROPROCESSOR
I
NTERFACE
B
LOCK
........................................................................ 45
7.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ......................................................................... 46
T
ABLE
13: XRT73R12 M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
............................................................................................................ 46
7.2 ASYNCHRONOUS AND SYNCHRONOUS DESCRIPTION .......................................................................... 47
T
ABLE
14: A
SYNCHRONOUS
T
IMING
S
PECIFICATIONS
............................................................................................................................. 48
F
IGURE
35. A
SYNCHRONOUS
μP I
NTERFACE
S
IGNALS
D
URING
P
ROGRAMMED
I/O R
EAD
AND
W
RITE
O
PERATIONS
.................................. 48
F
IGURE
36. S
YNCHRONOUS
μP I
NTERFACE
S
IGNALS
D
URING
P
ROGRAMMED
I/O R
EAD
AND
W
RITE
O
PERATIONS
.................................... 49
T
ABLE
15: S
YNCHRONOUS
T
IMING
S
PECIFICATIONS
............................................................................................................................... 49
7.3 REGISTER MAP ............................................................................................................................................. 50
T
ABLE
16: C
OMMAND
R
EGISTER
A
DDRESS
M
AP
,
WITHIN
THE
XRT73R12............................................................................................ 50
THE GLOBAL/CHIP-LEVEL REGISTERS ................................................................................................................59
REGISTER DESCRIPTION - GLOBAL REGISTERS ...............................................................................................59
T
ABLE
17: L
IST
AND
A
DDRESS
L
OCATIONS
OF
G
LOBAL
R
EGISTERS
........................................................................................................ 59
T
ABLE
18: APS/R
EDUNDANCY
T
RANSMIT
C
ONTROL
R
EGISTER
- CR0 (A
DDRESS
L
OCATION
= 0
X
00) ..................................................... 59
T
ABLE
19: APS/R
EDUNDANCY
T
RANSMIT
C
ONTROL
R
EGISTER
- CR8 (A
DDRESS
L
OCATION
= 0
X
08) ..................................................... 60
T
ABLE
20: C
HANNEL
L
EVEL
I
NTERRUPT
E
NABLE
R
EGISTER
- CR96 (A
DDRESS
L
OCATION
= 0
X
60)......................................................... 61
T
ABLE
21: C
HANNEL
L
EVEL
I
NTERRUPT
E
NABLE
R
EGISTER
- CR224 (A
DDRESS
L
OCATION
= 0
X
E0)....................................................... 62
T
ABLE
22: T
HE
ABOVE
IS
: C
HANNEL
L
EVEL
I
NTERRUPT
S
TATUS
R
EGISTER
- CR97 (A
DDRESS
L
OCATION
= 0
X
61) .................................. 63
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