參數(shù)資料
型號(hào)： XRT73R12IB
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
中文描述： DATACOM, PCM TRANSCEIVER, PBGA420
封裝： 35 X 35 MM, TBGA-420
文件頁(yè)數(shù)： 62/87頁(yè)
文件大?。?/td> 436K
代理商： XRT73R12IB
XRT73R12
REV. P1.0.3
PRELIMINARY
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
59
THE GLOBAL/CHIP-LEVEL REGISTERS
The register set, within the XRT73R12 contains ten global or chip-level registers. These registers control
operations in more than one channel or apply to the complete chip. This section will present detailed
information on the Global Registers.
REGISTER DESCRIPTION - GLOBAL REGISTERS
T
ABLE
17: L
IST
AND
A
DDRESS
L
OCATIONS
OF
G
LOBAL
R
EGISTERS
A
DDRESS
C
OMMAND
R
EGISTER
L
ABEL
T
YPE
R
EGISTER
N
AME
0x00
CR0
APST
R/W
APS Transmit Redundancy Control Register 0-5
0x08
CR8
APSR
R/W
APS Receive Redundancy Control Register 0-5
0x80
CR128
APST
R/W
APS Transmit Redundancy Control Register 6-11
0x88
CR136
APSR
R/W
APS Receive Redundancy Control Register 6-11
0x60
CR96
CIE
R/W
Channel 0-5 Interrupt Enable flags
0x61
CR97
CIS
R/O
Channel 0-5 Interrupt status flags
0xE0
CR224
CIE
R/W
Channel 6-11 Interrupt enable flags
0xE1
CR225
CIS
R/O
Channel 6-11 Interrupt status flags
0x6E
CR110
PN
ROM
Device Part Number Register
0x6F
CR111
VN
ROM
Chip Revision/Version Number Register
T
ABLE
18: APS/R
EDUNDANCY
T
RANSMIT
C
ONTROL
R
EGISTER
- CR0 (A
DDRESS
L
OCATION
= 0
X
00)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Reserved
Reserved
TxON Ch 5
TxON Ch 4
TxON Ch 3
TxON Ch 2
TxON Ch 1
TxON Ch 0
R/W
R/W
R/W
R/W
R/W
R/W
B
IT
N
UMBER
N
AME
T
YPE
D
ESCRIPTION
7,6
Reserved
5
4
3
2
1
0
TxON Ch 5
TxON Ch 4
TxON Ch 3
TxON Ch 2
TxON Ch 1
TxON Ch 0
R/W
Transmit Section ON - Channel n
This READ/WRITE bit-field is used to turn on or turn off the Transmit
Driver associated with Channel n. If the user turns on the Transmit
Driver, then Channel n will transmit DS3, E3 or STS-1 pulses on the
line via the TTIP_n and TRING_ n output pins.
Conversely, if the user turns off the Transmit Driver, then the TTIP_n
and TRING_n output pins will be tri-stated.
0 - Shuts off the Transmit Driver associated with Channel n and tri-
states the TTIP_n and TRING_ n output pins.
1 - Turns on the Transmit Driver associated with Channel n.
N
OTE
:
The master TxON control pin(pin # P4)
must
be in a high
state (logic 1) for this operation to turn on any channel.
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