參數(shù)資料
型號(hào): XRT75L00DIVTR-F
廠商: Exar Corporation
文件頁(yè)數(shù): 85/92頁(yè)
文件大小: 0K
描述: IC LIU E3/DS3/STS-1 SGL 52TQFP
標(biāo)準(zhǔn)包裝: 1,000
類(lèi)型: 線路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 1/1
規(guī)程: DS3,E3,STS-1,SONET
電源電壓: 3.135 V ~ 3.465 V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 52-LQFP
供應(yīng)商設(shè)備封裝: 52-TQFP(10x10)
包裝: 帶卷 (TR)
XRT75L00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.2
81
HOW MAJOR PATTERN A IS SYNTHESIZED
MAJOR PATTERN A is created (by the Mapper IC) by:
Repeating MINOR PATTERN P1 (e.g., 7 clock pulses, followed by a gap) 63 times.
Upon completion of the 63rd transmission of MINOR PATTERN P1, MINOR PATTERN P2 is transmitted
repeatedly 36 times.
Figure 60 presents an illustration which depicts the procedure that is used to synthesize MAJOR PATTERN A
Hence, MAJOR PATTERN A consists of "(63 x 7) + (36 x 5)" = 621 clock pulses. These 621 clock pulses were
delivered over a period of "(63 x 8) + (36 x 6)" = 720 STS-1 (or 51.84MHz) clock periods.
MAJOR PATTERN B
MAJOR PATTERN B consists of three sub or minor-patterns (which we will refer to as "MINOR PATTERNS P1,
P2 and P3).
MINOR PATTERN P1, which is used to partially synthesize MAJOR PATTERN B, is exactly the same "MINOR
PATTERN P1" as was presented above in Figure 30. Similarly, the MINOR PATTERN P2, which is also used
to partially synthesize MAJOR PATTERN B, is exactly the same "MINOR PATTERN P2" as was presented in
MINOR PATTERN P3 (which has yet to be defined) consists of a string of six (6) clock pulses, which contains
no gaps. An illustration of MINOR PATTERN P3 is presented below in Figure 61.
FIGURE 59. ILLUSTRATION OF MINOR PATTERN P2
FIGURE 60. ILLUSTRATION OF PROCEDURE WHICH IS USED TO SYNTHESIZE MAJOR PATTERN A
1
2
3
4
5
Missing Clock Pulse
MINOR PATTERN P1
MINOR PATTERN P2
Repeats 63 Times
Repeats 36 Times
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