參數(shù)資料
型號(hào): XRT75L03DIV
廠商: Exar Corporation
文件頁數(shù): 47/134頁
文件大?。?/td> 0K
描述: IC LIU E3/DS3/STS-1 3CH 128LQFP
標(biāo)準(zhǔn)包裝: 72
類型: 線路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 3/3
規(guī)程: DS3,E3,STS-1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 128-LQFP(14x20)
包裝: 托盤
XRT75L03D
á
REV. 1.0.0
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
2
TRANSMIT INTERFACE CHARACTERISTICS
Accepts either Single-Rail or Dual-Rail data from Terminal Equipment and generates a bipolar signal to the
line
Integrated Pulse Shaping Circuit
Built-in B3ZS/HDB3 Encoder (which can be disabled)
Accepts Transmit Clock with duty cycle of 30%-70%
Generates pulses that comply with the ITU-T G.703 pulse template for E3 applications
Generates pulses that comply with the DSX-3 pulse template, as specified in Bellcore GR-499-CORE and
ANSI T1.102_1993
Generates pulses that comply with the STSX-1 pulse template, as specified in Bellcore GR-253-CORE
Transmitter can be turned off in order to support redundancy designs
RECEIVE INTERFACE CHARACTERISTICS
Integrated Adaptive Receive Equalization (optional) for optimal Clock and Data Recovery
Declares and Clears the LOS defect per ITU-T G.775 requirements for E3 and DS3 applications
Meets Jitter Tolerance Requirements, as specified in ITU-T G.823_1993 for E3 Applications
Meets Jitter Tolerance Requirements, as specified in Bellcore GR-499-CORE for DS3 Applications
Declares Loss of Signal (LOS) and Loss of Lock (LOL) Alarms
Built-in B3ZS/HDB3 Decoder (which can be disabled)
Recovered Data can be muted while the LOS Condition is declared
Outputs either Single-Rail or Dual-Rail data to the Terminal Equipment
FIGURE 1. BLOCK DIAGRAM OF THE XRT 75L03D
HO S T /H W
S T S -1/DS 3_(n )
E3 _(n )
RE Q E N_(n )
RT IP _(n )
RRin g _(n )
SR /D R
X R T 75L 03 D
RL B_(n )
RL O S _(n )
JA T x/R x
T P Data_ (n)
T NData_(n )
TxC lk_ (n )
TAO S _(n)
TxLE V _ (n )
TxO N _(n)
C h annel 2
C h annel 0
Ch an n el 1
N o te s: 1.
(n ) = 0, 1 o r 2 fo r resp ec tive C h an n els
2. S eria l P roce s sor In terface input pins a re sh a re d by th e th ree C h annels in " H os t" M ode and redefined in th e "H a rd w a re" M ode.
Device
Monitor
MT IP _(n)
MR in g_ (n )
DM O _(n )
Tim in g
Contro l
TTIP _(n )
TR in g_ (n )
Tx
Pu lse
Sh apin g
HDB 3/
B3 ZS
En co der
RL O L _(n )
RxO N
RxClkIN V
RxClk_ (n )
R P OS _(n)
R N E G _ (n)/
LC V _ (n )
Tx
Control
Jitter
A tte nua to r
MU X
Line
Driver
LO S T H R
LLB _(n)
Invert
Rem o te
Lo opB ack
HDB 3/
B3 ZS
Decoder
MU X
AG C/
Eq ualizer
Pe ak Detector
LO S
Detector
Slice r
Jitter
Attenu ator
Se rial
Proce ssor
Inte rfa ce
Lo cal
Lo op Ba ck
Clock & Data
Rec overy
Clock
S ynthe sizer
E 3Clk,D S 3Clk,
ST S -1C lk
RE S E T
CS
SC lk
IN T
SD O
SD I
CL KO U T
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