- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9992 > XRT75R06DIB (Exar Corporation)IC LIU E3/DS3/STS-1 6CH 217BGA PDF資料下載
參數(shù)資料
| 型號(hào)： | XRT75R06DIB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 87/105頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E3/DS3/STS-1 6CH 217BGA |
| 標(biāo)準(zhǔn)包裝： | 126 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動(dòng)器/接收器數(shù)： | 6/6 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 217-BBGA |
| 供應(yīng)商設(shè)備封裝： | 217-BGA（23x23） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁當(dāng)前第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁
XRT75R06D
á
REV. 1.0.0
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
77
8.3.4
Why are we talking about Pointer Adjustments?
The overall SONET network consists of numerous "Synchronization Islands". As a consequence, whenever a
SONET signal is being transmitted from one "Synchronization Island" to another; that SONET signal will
undergo a "clock domain" change as it traverses the network. This clock domain change will result in periodic
pointer-adjustments occurring within this SONET signal. Depending upon the direction of this "clock-domain"
shift that the SONET signal experiences, there will either be periodic "incrementing" pointer-adjustment events
or periodic "decrementing" pointer-adjustment events within this SONET signal.
Regardless of whether a given SONET signal is experiencing incrementing or decrementing pointer
adjustment events, each pointer adjustment event will result in an abrupt 8-bit shift in the position of the SPE
within the STS-1 data-stream. If this STS-1 signal is transporting an "asynchronously-mapped" DS3 signal;
then this 8-bit shift in the location of the SPE (within the STS-1 signal) will result in approximately 8UIpp of jitter
within the asynchronously-mapped DS3 signal, as it is de-mapped from SONET. In “Section 8.5, A Review of
we will discuss the "Category I Intrinsic Jitter Requirements (for DS3 Applications) per Telcordia GR-253-
CORE. However, for now we will simply state that this 8UIpp of intrinsic jitter far exceeds these "intrinsic jitter"
requirements.
In summary, pointer-adjustments events are a "fact of life" within the SONET/SDH network. Further, pointer-
adjustment events, within a SONET signal that is transporting an asynchronously-mapped DS3 signal, will
impose a significant impact on the Intrinsic Jitter and Wander within that DS3 signal as it is de-mapped from
SONET.
8.4
Clock Gapping Jitter
In most applications (in which the LIU will be used in a SONET De-Sync Application) the user will typically
interface the LIU to a Mapper Device in the manner as presented below in Figure 56.
In this application, the Mapper IC will have the responsibility of receiving an STS-N signal (from the SONET
Network) and performing all of the following operations on this STS-N signal.
Byte-de-interleaving this incoming STS-N signal into N STS-1 signals
Terminating each of these STS-1 signals
Extracting (or de-mapping) the DS3 signal(s) from the SPEs within each of these terminated STS-1 signals.
In this application, these Mapper devices can be thought of as multi-channel devices. For example, an STS-3
Mapper can be viewed as a 3-Channel DS3/STS-1 to STS-3 Mapper IC. Similarly, an STS-12 Mapper can be
FIGURE 56. ILLUSTRATION OF THE TYPICAL APPLICATIONS FOR THE LIU IN A SONET DE-SYNC APPLICATION
DS3 to STS-N
Mapper/
Demapper
IC
DS3 to STS-N
Mapper/
Demapper
IC
LIU
STS-N Signal
TPDATA_n input pin
TCLK_n input
De-Mapped (Gapped)
DS3 Data and Clock
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-B1T-MW-F1 | CONVERTER MOD DC/DC 6.5V 100W |
| VI-23X-IU-F4 | CONVERTER MOD DC/DC 5.2V 200W |
| IDT72V3623L10PF | IC FIFO SYNC 1KX9 10NS 128QFP |
| IDT72V835L15PF | IC FIFO SYNC 2048X18 128QFP |
| XRT75L04IV | IC LIU E3/DS3/STS-1 4CH 176LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT75R06DIB-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 6 Channel 3.3V-5V temp -45 to 85C RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT75R06ES | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 6CH T3/E3/STS1LIU+JA 3.3V W/REDUNDANCY RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT75R06IB | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 6CH E3/DS3/STS1 LIU+Jitter Attenuato RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT75R06IB208 | 制造商:Exar Corporation 功能描述:Line Interface Unit 51.84Mbps DS3/E3/STS-1 Parallel 217-Pin BGA |
| XRT75R06IB-F | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 6 Channel 3.3V-5V temp -45 to 85C RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。