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參數(shù)資料
型號(hào): XRT75R12DIB-L
廠商: Exar Corporation
文件頁數(shù): 26/133頁
文件大?。?/td> 0K
描述: IC LIU E3/DS3/STS-1 12CH 420TBGA
標(biāo)準(zhǔn)包裝: 40
類型: 線路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 12/12
規(guī)程: DS3,E3,STS-1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 420-LBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 420-TBGA(35x35)
包裝: 托盤
XRT75R12D
117
REV. 1.0.3
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
Using a particular clock edge within the "gapped" clock signal (from the Mapper IC) to sample and latch the
value of each DS3 data-bit that is output from the Mapper IC.
To (through the user of the Jitter Attenuator block) attenuate the jitter within this "DS3 data" and "clock signal"
that is output from the Mapper IC.
To convert this "smoothed" DS3 data and clock into industry-compliant DS3 pulses, and to output these
pulses onto the line.
To configure the LIU to operate in the correct mode for this application, the user must execute the following
configuration steps.
a. Configure the LIU to operate in the DS3 Mode
The user can configure a given channel (within the LIU) to operate in the DS3 Mode, by executing the following
step.
If the LIU has been configured to operate in the Host Mode
The user can accomplish this by clearing both Bits 2 (E3_n) and Bits 1 (STS-1/DS3*_n), within each of the
"Channel Control Registers" to "0" as depicted below.
b. Configure the LIU to operate in the Single-Rail Mode
Since the Mapper IC will typically output a single "Data Line" and a "Clock Line" for each DS3 signal that it
demaps from the incoming STS-N signal, it is imperative to configure each channel within the LIU to operate in
the Single Rail Mode.
The user can accomplish this by executing the following step.
If the LIU has been configured to operate in the Host Mode
The user can accomplish this by setting Bit 0 (SR/DR*), within the each of the "Channel Control" Registers to
"1", as illustrated below.
TABLE 45: CHANNEL CONTROL REGISTER - CHANNEL N, ADDRESS LOCATION; 0XM6 (M = 0-5 & 8-D) (N = [0:11])
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
PRBS Enable
Ch_n
RLB_n
LLB_n
E3_n
STS-1/DS3_n
SR/DR_n
R/O
R/W
0
TABLE 46: CHANNEL CONTROL REGISTER - CHANNEL N, ADDRESS LOCATION; 0XM6 (M = 0-5 & 8-D) (N = [0:11])
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
PRBS Enable
Ch_n
RLB_n
LLB_n
E3_n
STS-1/
DS3_n
SR/DR_n
R/O
R/W
0
1
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