VCC GND CLK2 V
參數(shù)資料
型號: XRT8000ID-F
廠商: Exar Corporation
文件頁數(shù): 18/24頁
文件大小: 0K
描述: IC WAN CLOCK E1/E1 DUAL 18SOIC
標(biāo)準(zhǔn)包裝: 20
類型: 時鐘/頻率發(fā)生器,同步器,多路復(fù)用器
PLL:
主要目的: 電信
輸入: 時鐘
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 無/無
頻率 - 最大: 2.048MHz
電源電壓: 3.135 V ~ 5.25 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 18-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 18-SOIC
包裝: 管件
其它名稱: 1016-1580-5
XRT8000ID-F-ND
XRT8000
3
Rev. 1.11
PIN CONFIGURATION
SCLK
CSB
SDI
VCC
GND
CLK2
VCC
LOCKDET
SDO
SYNC
FIN
GND
CLK1
VCC
MSB
VCC
GND
18 Lead PDIP (0.300”)
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
18 Lead SOIC (Jedec, 0.300”)
SCLK
CSB
SDI
VCC
GND
CLK2
VCC
LOCKDET
SDO
SYNC
FIN
GND
CLK1
VCC
MSB
VCC
GND
18
1
10
9
2
3
4
5
6
7
15
14
13
12
11
17
16
8
PIN DESCRIPTION
Symbol
Pin#
Type
Description
SDO
1
O
Serial Data Output (Microprocessor Serial Interface). Data output from the command reg-
isters.
SYNC
2
O
An 8kHz Signal SubDivided From FIN. This output can be threestated via CR5. SYNC can
be used to synchronize other XRT8000 which are configured in slave modes.
FIN
3
I
Reference Frequency Input.
GND
4
Digital Ground.
GND
5
Digital Ground.
CLK1
6
O
Clock 1. Output of the phase-locked loop 1.
VCC
7
Digital Positive Power Supply.
MSB
8
I
Master/Slave Mode Select Input. If this input is high, then the MASTER mode is selected. If
this input is low, then the SLAVE mode is enabled. This pin is internally pulled up via 100KW
resistor.
GND
9
Analog Ground.
VCC
10
Analog Positive Supply.
LOCKDET
11
O
Lock Detect. This output is high when both phase-locked loops are in lock and will go low if
either one of the phase locked loops loses lock.
VCC
12
Digital Positive Power Supply.
CLK2
13
O
Clock 2. Output of the phase-locked loop 2.
GND
14
Digital Ground.
VCC
15
Digital Positive Power Supply.
SDI
16
I
Serial Data Input (Microprocessor Serial Interface) Data input to the command registers.
CSB
17
I
Chip Select Not (Microprocessor Serial Interface) . When this input is low the data in and
out will be shifted in the appropriate registers. Internal pull up (100K).
SCLK
18
I
Serial Clock Input (Microprocessor Serial Interface) . This clock will serve as a reference
to the data streams to SDI and SDO (the positive edge of SCLK is used to latch the data).
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