PIN #
參數(shù)資料
型號(hào): XRT82D20IW
廠商: Exar Corporation
文件頁(yè)數(shù): 22/27頁(yè)
文件大?。?/td> 0K
描述: IC LIU EI SGL 28SOJ
標(biāo)準(zhǔn)包裝: 27
類(lèi)型: 線(xiàn)路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 1/1
規(guī)程: E1
電源電壓: 3.135 V ~ 3.465 V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 28-BSOJ
供應(yīng)商設(shè)備封裝: 28-SOJ
包裝: 管件
XRT82D20
3
SINGLE CHANNEL E1 LINE INTERFACE UNIT
REV. 1.0.8
PIN DESCRIPTIONS
PIN #
SYMBOL
TYPE
DESCRIPTION
1
RLOS
O
Receiver Loss of Signal: This pin toggles Low to indicate the loss of signal at the
receive inputs.
2
ClkLOS
O
Receiver Loss of Clock: With MuteRx=1, this pin will toggle low to indicate a loss
of clock has occurred when the receive signal is lost (RLOS=0). When RLOS=0, no
transitions occur on RClk, RPOS/RData and RNEG outputs.
3
TNEG/
CODE
I
Transmitter Negative Data Input/Coding Select: With Jitter Attenuator enabled
(pin 18=1), input activity on this pin determines whether the device is configured to
operate in single-rail or dual-rail mode. With n-rail transmit data applied to this pin,
the device is automatically configured to operate in dual-rail mode for both transmit
input and receive output.
If this pin is tied high for more than 16 clock cycles, the device is configured to oper-
ate in single-rail mode with HDB3 encoding and decoding functions enabled.
If this pin is tied low for more than 16 clock cycles, the device is configured to oper-
ate in single-rail mode with AMI encoding and decoding functions enabled. (internal
pull-down).
4
RNEG/LCV
O
Receive Negative Data/Line Code Violation Output:
If the device is configured in Dual-rail mode with n-rail data applied to pin 3, then the
receive negative data will be output through this pin.
If the device is configured in Single-rail mode and operate with HDB3 coding
enabled, HDB3 code violation will be detected and cause this pin to go high.
If the device is configured in Single-rail mode and with AMI coding selected, every
bipolar violation will be reported at this pin.
5
RClk
O
Receive Clock:
Output receive clock signal to the terminal equipment.
6
RPOS/
RData
O
Receive Positive/ Data Output:
In Dual-rail mode, this signal is the p-rail receive output data. In Single-rail mode,
this signal is the receive output data.
7
TClk
I
Transmitter Clock Input:
Input clock signal (2.048 MHz ± 50ppm)
8
TPOS/
TData
I
Transmit Positive / Data Input:
In Dual-rail mode, this signal is the p-rail transmit input data. In Single-rail mode,
this signal is the transmit input data.
9
LLoop
I
Local Loop back enable (active low):
Tie this pin low to enable analog Local Loop-back.In local loop-back mode, transmit
output data is looped back to the input of the receiver.Input signal at RTIP and
RRing are ignored. Local Loop-back has priority over Remote and Digital Loop-
back mode. See
for more details. (internal pull-up).
10
RLoop
I
Remote Loop Back Enable (active low):
Connect this pin to ground to enable Remote Loop-back. In Remote Loop-back
mode, transmit data at TPOS/TData and TNEG are ignored. See
The Remote Loop Back Mode” on page 24 for more details. (internal pull-
up).
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