
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
(510) 668-7000
FAX (510) 668-7001
www.exar.com
PRELIMINARY
XRT82L38
OCTAL E1/T1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
JANUARY 2001
REV. P1.0.5
GENERAL DESCRIPTION
XRT82L38 is a fully integrated octal (eight channels)
short-haul line interface unit for T1(1.544Mbps) 100
and E1(2.048Mbps) 75
or 120
applications. Each
channel consists of a receiver with equalizer for reli-
able data and clock recovery, and a transmitter which
accepts either a single or dual-rail digital inputs for
signal transmission to the line using a low impedance
line driver. The device also includes a crystal-less jit-
ter attenuator which, depending on system require-
ment, can be selected in the receive or transmit
path through the Host or Hardware Mode control.
The XRT82L38 can be configured as a 7 channel line
interface with the eighth channel used for ITU-G.772
compliant protected monitoring purposes. This device
uses a low power CMOS design and requires only a
single 3.3V supply and all digital inputs are 5V toler-
ant.
FEATURES
Fully integrated octal, short-haul PCM transceivers
for T1 and E1 applications.
On Chip Receive Equalizer and Transmit Pulse
Shaper for DS1 Digital Cross Connect(DSX-1) and
CEPT 75
and 120
line terminations
On chip clock recovery circuit
Transformer or capacitor coupled receiver inputs
Crystal-less jitter attenuator can be selected in the
transmit or receive path
High receiver interference immunity
Per-channel transmit power shutdown
Tri-state transmit output capability
Supports the same type transformer for both T1
and E1 line interface
On chip per-channel driver failure monitoring circuit
On chip HDB3/B8ZS/AMI encoder/decoder func-
tions
Transmit return loss meet or exceeds ETSI 300 166
standard
Meets or exceeds specifications in ITU G.703,
G.775, G.736 and G.823; Bellcore GR-499-CORE;
ANSI T1.403 and ETSI 300-166
JTAG Boundary Scan test port per IEEE1149.1
G.772 Monitoring Capability
Single +3.3V Supply Operation
3.3V or 5.0V logic Level inputs
144 pin thermally enhanced TQFP Package
APPLICATIONS
Digital cross connects(DSX-1)
Channel Banks
High speed data transmission line cards
T1/E1 Multiplexer
Public switching systems and PBX interfaces
F
IGURE
1. B
LOCK
D
IAGRAM
OF
THE
XRT82L38
μ
P Controller &
Hardware Interface
TxClk[n]
TxPOS[n] / TDATA[n]
TxNEG[n]
RxClk[n]
RxPOS[n]/ RDATA[n]
RxNEG[n]/ LCV[n]
RxLOS[n]
HDB3/
EB8Z8
MUX
Tx/Rx Jitter
Attenuator
Tx
Timing
Tx Pulse
Shaper
MUX
Line
Driver
Tx/Rx Jitter
Attenuator
Data & Timing
Recovery
Peak
Detector
& Slicer
Rx
Equalizer
LOS
HDB3/
B8Z8
Decoder
Clock
Generator
MClk
Enable/
Disable
RTIP[n]
RRing[n]
Remote
LoopBack
Local
Analog
LoopBack
LDigital
One of eight channels
Driver
Monitor
JTAG
TDI
TCK
TMS
TDO
INT/RxJA
RDY_DTACK/TxJA
PCLK
WR_R/W/FIFO
CS/ECC
ALE_AS/ECB
RD_DS/ECA
A[0]/LOOPSEL
A[1:4]
LOOPEN[0:7/D[0:7]
HW/HOST
PTS1/ClkE
PTS2/SR_DR
ICT
TVDD[n]
TTIP[n]
TRing[n]
TGND[n]