參數(shù)資料
型號: XRT83D10IWTR
廠商: Exar Corporation
文件頁數(shù): 4/18頁
文件大?。?/td> 0K
描述: IC LIU T1/E1 SGL 28SOJ
標(biāo)準(zhǔn)包裝: 1,000
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: T1,E1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 28-BSOJ
供應(yīng)商設(shè)備封裝: 28-SOJ
包裝: 帶卷 (TR)
XRT83D10
xr
SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT
REV. 1.0.3
12
1.3
JITTER ATTENUATOR
To reduce frequency jitter in the transmit clock or receive clock, a crystal-less jitter attenuator is provided. The
jitter attenuator can be selected either in the transmit or receive path or it can be disabled as shown in Table 8.
1.3.1
FIFO Overflow Signal (FOFS):
A FIFO overflow Signal (FOFS = 1) is indicated if the phase jitter exceeds the tolerance of the jitter attenuator.
When FOFS is "High", jitter attenuator bandwidth is increased to track the short term jitter and no data error will
FIGURE 7. ITU G.703 PULSE TEMPLATE
TABLE 8: JITTER ATTENUATOR SELECTION
JITTER ATTENUATOR CONNECTIVITY
MODE 1MODE 2
Bypass (Disabled)
0
Transmit Path
0
1
Receive Path
1
0
Test Mode
1
10%
269 ns
(244 + 25)
194 ns
(244–50)
244 ns
219 ns
(244 – 25)
488 ns
(244 + 244)
0%
50%
20%
V = 100%
Nominal pulse
Note – V corresponds to the nominal peak value.
20%
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