
XRT85L61
xr
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.2
3
PIN DESCRIPTIONS
PIN #
SYMBOL
TYPE
DESCRIPTION
1
MCLK1
I
Reference T1 Clock input:
This signal is an independent 1544 kHz clock with accuracy better than
+ 32 ppm and duty cycle within 40% to 60%. This clock provides timing
source for the PLL clock recovery circuit in T1 mode. This signal must be
available for the device to operate.
2
JAEN
I
Jitter Attenuator Enable:
Tie this pin “High” to enable the Jitter Attenuator. When enabled, a 32 bit
FIFO is included in the data path for all modes of operation.
NOTE: Internally Pulled down with 50 k
resistor
3
MCLK2
I
Reference E1 and 64 kHz Clock Input:
This signal is an independent 2048 kHz clock with accuracy better than +
50 ppm and duty cycle within 40% to 60%. This clock provides timing
source for the PLL clock recovery circuit in E1 and 64 kHz mode. This
signal must be available for the device to operate.
NOTE: To reduce intrinsic jitter when JA is enabled, it is recommended to
have reference clock with an accuracy of ± 25 ppm or better.
4
JAVDD
***
VDD for Jitter Attenuator (3.3V ± 5%)
5
JAGND
***
Jitter Attenuator Ground
6
ICT
I
In circuit Testing
When this pin is grounded, all output pins are Tri-stated for testing pur-
poses.
NOTE: Internally Pulled up with 50 k
resistor
7
RTIP
I
Receive Positive Input
8
RRING
I
Receive Negative Input
9
AVDD
***
Analog VDD (3.3V ± 5%)
10
AGND
***
Analog Ground
11
S1
I
Mode Select
NOTE: T1 NRZ or E1 NRZ means the output data at RPOS and RNEG
are 1 RCLK wide.
S2
S3
0
1
0
1
MODE
64 kHz + 8 kHz
64kHz+8kHz+400Hz
E1 RZ
E1 NRZ
S1
0
1
T1
T1 (output full width data)
E1 (output full width data)
Reserved
1
0