TABLE
參數(shù)資料
型號： XRT86VL32IB-F
廠商： Exar Corporation
文件頁數(shù)： 150/155頁
文件大?。?/td> 0K
描述： IC LIU/FRAMER T1/E1/J1 2CH 225BG
標(biāo)準(zhǔn)包裝： 84
控制器類型： T1/E1/J1 調(diào)幀器，LIU
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 225-BGA
供應(yīng)商設(shè)備封裝： 225-BGA（19x19）
包裝： 托盤
XRT86VL32
89
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
REV. V1.2.0
TABLE 79: BLOCK INTERRUPT ENABLE REGISTER (BIER)
HEX ADDRESS: 0XnB01
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
Reserved
For E1 mode only
6
LBCODE_ENB
R/W
0
Loopback Code Block interrupt enable
This bit permits the user to either enable or disable the Loopback
Code Interrupt Block for interrupt generation.
Writing a “0” to this register bit will disable the Loopback Code Block
for interrupt generation, all Loopback Code interrupts will be dis-
abled for interrupt generation.
If the user writes a “1” to this register bit, the Loopback Code Inter-
rupts at the “Block Level” will be enabled. However, the individual
Loopback Code interrupts at the “Source Level” still need to be
enabled to in order to generate that particular interrupt to the inter-
rupt pin.
0 - Disables all Loopback Code Interrupt Block interrupt within the
device.
1 - Enables the Loopback Code interrupt at the “Block-Level”.
5
RXCLKLOSS
R/W
0
Loss of Recovered Clock Interrupt Enable
This bit permits the user to either enable or disable the Loss of
Recovered Clock Interrupt for interrupt generation.
0 - Disables the Loss of Recovered Clock Interrupt within the device.
1 - Enables the Loss of Recovered Clock interrupt at the “Source-
Level”.
4
ONESEC_ENB
R/W
0
One Second Interrupt Enable
This bit permits the user to either enable or disable the One Second
Interrupt for interrupt generation.
0 - Disables the One Second Interrupt within the device.
1 - Enables the One Second interrupt at the “Source-Level”.
3
HDLC_ENB
R/W
0
HDLC Block Interrupt Enable
This bit permits the user to either enable or disable the HDLC Block
for interrupt generation.
Writing a “0” to this register bit will disable the HDLC Block for inter-
rupt generation, all HDLC interrupts will be disabled for interrupt
generation.
If the user writes a “1” to this register bit, the HDLC Block interrupt at
the “Block Level” will be enabled. However, the individual HDLC
interrupts at the “Source Level” still need to be enabled in order to
generate that particular interrupt to the interrupt pin.
0 - Disables all SA6 Block interrupt within the device.
1 - Enables the SA6 interrupt at the “Block-Level”.
相關(guān)PDF資料
PDF描述
XRT86VL34IB-F IC LIU/FRAMER T1/E1/J1 4CH 225BG
XRT86VL38IB484-F IC LIU/FRAMER T1/E1/J1 8CH 484BG
XRT86VX38IB329-F IC TI/E1/J1 FRAMER/LIU 329FPBGA
XRT94L31IB-L IC MAPPER DS3/E3/STS-1 504TBGA
XRT94L33IB-L IC MAPPER DS3/E3/STS-1 504TBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT86VL34 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
XRT86VL34_07 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
XRT86VL34_1 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
XRT86VL34_2 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
XRT86VL34ES 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*