XRT86VL38
III
OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
REV. V1.2.1
LIST OF TABLES
Table 1:: Register Summary ..............................................................................................................................................6
Table 2:: Clock Select Register (CSR) Hex Address: 0xn100 ..................12
Table 3:: Line Interface Control Register (LICR) Hex Address: 0xn101 ....................14
Table 4:: General Purpose Input/Output 0 Control Register (GPIOCR0) Hex Address: 0x0102 ......................16
Table 5:: General Purpose Input/Output 1 Control Register (GPIOCR1) Hex Address: 0x4102 .......................17
Table 6:: Framing Select Register (FSR) Hex Address: 0xn107 ................18
Table 7:: Alarm Generation Register (AGR) Hex Address: 0xn108 ...................22
Table 8:: Synchronization MUX Register (SMR) Hex Address: 0xn109 .................24
Table 9:: Transmit Signaling and Data Link Select Register (TSDLSR) Hex Address:0xn10A ....................27
Table 10:: Framing Control Register (FCR) Hex Address: 0xn10B ...............30
Table 11:: Receive Signaling & Data Link Select Register (RSDLSR) Hex Address: 0xn10C ................32
Table 12:: Receive Signaling Change Register 0 (RSCR 0) Hex Address: 0xn10D ............34
Table 13:: Receive Signaling Change Register 1 (RSCR 1) Hex Address: 0xn10E ...........34
Table 14:: Receive Signaling Change Register 2 (RSCR 2) Hex Address: 0xn10F ...........34
Table 15:: Receive Signaling Change Register 3 (RSCR 3) Hex Address: 0xn110 ..........35
Table 16:: Receive National Bits Register (RNBR) Hex Address: 0xn111 ...............36
Table 17:: Receive Extra Bits Register (REBR) Hex Address: 0xn112 ..............37
Table 18:: Data Link Control Register (DLCR1) Hex Address: 0xn113 ..................39
Table 19:: Transmit Data Link Byte Count Register (TDLBCR1) Hex Address: 0xn114 ...............41
Table 20:: Receive Data Link Byte Count Register (RDLBCR1) Hex Address: 0xn115 ................42
Table 21:: Slip Buffer Control Register (SBCR) Hex Address: 0xn116 ...................43
Table 22:: FIFO Latency Register (FFOLR) Hex Address: 0xn117 ...............44
Table 23:: DMA 0 (Write) Configuration Register (D0WCR) Hex Address: 0xn118 .................45
Table 24:: DMA 1 (Read) Configuration Register (D1RCR) Hex Address: 0xn119 ................46
Table 25:: Interrupt Control Register (ICR) Hex Address: 0xn11A ..................47
Table 26:: LAPD Select Register (LAPDSR) Hex Address: 0xn11B ................48
Table 27:: Performance Report Control Register (PRCR) Hex Address: 0xn11D ...................48
Table 28:: Gapped Clock Control Register (GCCR) Hex Address: 0xn11E .................49
Table 29:: Transmit Interface Control Register (TICR) Hex Address:0xn120 ...................50
Table 30:: Transmit Interface Speed When Multiplexed Mode is Disabled (TxMUXEN = 0) ...........................................52
Table 31:: Transmit Interface Speed when Multiplexed Mode is Enabled (TxMUXEN = 1) ............................................53
Table 32:: PRBS Control And Status Register 0 (PRBSCSR0) Hex Address: 0xn121 ................54
Table 33:: Receive Interface Control Register (RICR) Hex Address: 0xn122 ..................56
Table 34:: Receive Interface Speed When Multiplexed Mode is Disabled (TxMUXEN = 0) ............................................58
Table 35:: Receive Interface Speed when Multiplexed Mode is Enabled (TxMUXEN = 1) .............................................59
Table 36:: PRBS Control and Status Register 1 (PRBSCSR1) Hex Address: 0xn123 .................60
Table 37:: Loopback Code Control Register (LCCR) Hex Address: 0xn124 ..................62
Table 38:: Transmit Loopback Coder Register (TLCR) Hex Address: 0xn125 .................62
Table 39:: Receive Loopback Activation Code Register (RLACR) Hex Address: 0xn126 ...............62
Table 40:: Receive Loopback Deactivation Code Register (RLDCR) Hex Address: 0xn127 ...................62
Table 41:: Defect Detection Enable Register (DDER) Hex Address: 0xn129 ...................62
Table 42:: Transmit Sa Select Register (TSASR) Hex Address: 0xn130 ................63
Table 43:: Transmit Sa Auto Control Register 1 (TSACR1) Hex Address: 0xn131 ...................65
Table 44:: Conditions on Receive side When TSACR1 bits Are enabled ........................................................................66
Table 45:: Transmit Sa Auto Control Register 2 (TSACR2) Hex Address: 0xn132 ......................67
Table 46:: Conditions on Receive side When TSACR2 bits enabled ..............................................................................68
Table 47:: Transmit Sa4 Register (TSA4R) Hex Address: 0xn133 .............69
Table 48:: Transmit Sa5 Register (TSA5R) Hex Address: 0xn134 .............69
Table 49:: Transmit Sa6 Register (TSA6R) Hex Address: 0xn135 .............69
Table 50:: Transmit Sa7 Register (TSA7R) Hex Address: 0xn136 .............69
Table 51:: Transmit Sa8 Register (TSA8R) Hex Address: 0xn137 .............70
Table 52:: Receive Sa4 Register (RSA4R) Hex Address: 0xn13B .............71
Table 53:: Receive Sa5 Register (RSA5R) Hex Address: 0xn13C .............71
Table 54:: Receive Sa6 Register (RSA6R) Hex Address: 0xn13D .............71
Table 55:: Receive Sa7 Register (RSA7R) Hex Address: 0xn13E .............72
Table 56:: Receive Sa8 Register (RSA8R) Hex Address: 0xn13F .............72
Table 57:: Data Link Control Register (DLCR2) Hex Address: 0xn143 ..............73
Table 58:: Transmit Data Link Byte Count Register (TDLBCR2) Hex Address: 0xn144 ...............75