參數(shù)資料
型號: XRT91L34IVTR
廠商: Exar Corporation
文件頁數(shù): 36/38頁
文件大小: 0K
描述: IC MULTIRATE CDR QUAD 128LQFP
標準包裝: 750
類型: 時鐘和數(shù)據(jù)恢復(fù)(CDR),扇出緩沖器(分配),多路復(fù)用器
PLL:
主要目的: SONET/SDH,STS,STM
輸入: LVDS,LVPECL
輸出: LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 622.08MHz
電源電壓: 1.71 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-LQFP(14x14)
包裝: 帶卷 (TR)
XRT91L34
7
REV. 1.0.1
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
CDRREFSEL
LVTTL,
LVCMOS
I
119
Clock and Data Recovery Unit Reference Frequency Select
Selects the Clock and Data Recovery Unit reference frequency
on REFCLKP/N pins or TTLREFCLK pin based on the table
below.
"Low" = 77.76 MHz reference clock
"High" = 19.44 MHz reference clock
NOTE: REFCLKP/N or TTLREFCLK input should be generated
from a crystal oscillator which has a frequency
accuracy better than 100ppm in order for the received
data rate frequency to have the necessary accuracy
required for SONET systems.
NOTE: This pin has no function in Host Mode.
This pin is provided with an internal pull-down.
OUTCFG
LVTTL,
LVCMOS
I
44
Output Configuration
Globally selects recovered clock and data outputs to be LVDS
or Differential LVPECL on all four channels based on table
below.
"Low" = LVDS Standard Output
"High" = Differential LVPECL Standard Output
This pin is provided with an internal pull-down.
CDRDIS0
CDRDIS1
CDRDIS2
CDRDIS3
LVTTL,
LVCMOS
I
107
106
56
55
Clock and Data Recovery Unit Disable
Active "High." Disables internal Clock and Data Recovery unit
for respective channel.
This enables lower power operation
when channel is unused.
"Low" = Internal CDR unit is Enabled
"High" = Internal CDR unit is Disabled
NOTE: These pins have no function in Host Mode.
These pins are provided with internal pull-down.
NAME
LEVEL
TYPE
PIN
DESCRIPTION
CDRREFSEL
REFCLKP/N OR
TTLREFCLK
FREQUENCY
CHANNEL 0 - 3
AVAILABLE DATA RATES
0
77.76 MHz
STS-12/STM-4 622.08 Mbps
STS-3/STM-1 155.52 Mbps
STS-1/STM-0 51.84 Mbps
1
19.44 MHz
OUTCFG
Input
Configuration
Output
Configuration
0
LVDS/
Differential LVPECL
LVDS
1
LVDS/
Differential LVPECL
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