- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376464 > XRT94L33 (Exar Corporation) highly integrated SONET/SDH terminator PDF資料下載
參數(shù)資料
| 型號： | XRT94L33 |
| 廠商： | Exar Corporation |
| 英文描述： | highly integrated SONET/SDH terminator |
| 中文描述： | 高度集成的SONET / SDH終結(jié)者 |
| 文件頁數(shù)： | 4/7頁 |
| 文件大?。?/td> | 180K |
| 代理商： | XRT94L33 |
XRT94L43
SONET/SDH STS-12/STM-4 12 E3/DS3/STS-1 MAPPER
REV. P1.0.0
xr
PRELIMINARY
4
HDLC controller complies with ITU-T Q.921 LAPD
protocol
Provides Line and Local Loopbacks
Supports M13 and C-bit parity mode
Supports B3ZS line decoding which can be user
enabled. Replaces valid B0V or 00V with 3 zeros
Synchronizes to incoming frame based upon 10
valid F bits followed by 3 consecutive valid M
frames. Offers optional AIC-bit or parity verification
before declaration of sync
Detects Out of Frame (OOF) upon 3 or 6 F bits out
of 15 F bits in error or 1 or more M bits in 3 of 4 con-
secutive frames in error
Detects Loss of Signal (LOS) upon encountering
180 consecutive 0’s and clears on at least 60 of
successive received 1’s.Offers optional disable
Detects idle state by checking C-bit in subframe 3
are all zero, X-bits are one and repeating 11001100
payloads. Declaration occurs when all the above
conditions persist for 63 M-frames. Clears the con-
dition when 63 valid M-frames are received
Detects AIS with different algorithm
Calculate parity and compare
Validate FERF bits, sets to one when both X-bits
are zero and clears when they are One
Detects and validates FEAC codes upon 8 out of 10
last identical received codes. Invalidates on 3 in 10
mismatch
Provides 15-bit PRBS lock
DS3 TRANSMIT FRAMER
Offers following frame generation mechanism:
Asynchronous operation, using receive side clock,
external framing
Supports either C-bit operation or M13 operation:
optional all C bits set to "1" or C-bit parity ID bit
(C11) toggled in each frame for M13 operation
Provides start of frame control with external pin
Inserts frame overhead bits via External serial port
or Internal generation
Generates and checks parity
Enables FERF insertion by receiver LOS and/or
OOF and/or AIS conditions with polarity suitability
Enables FEBE insertion through register bit. Indi-
cates receiver F-bit errors, M-bit errors and CP-bit
parity errors
Provides FEAC channel processing including gen-
eration of valid FEAC patterns and transmissions of
all 1’s upon programming of idle code
Inserts path maintenance data link through HDLC
transmitter which contains the following features:
AM for storage of entire LAPD message
Selection of message length to 82 or 76
bytes
Optional frame header generation
Generation of flag sequences
Computation and insertion of CRC
Zero stuffing
Register bits for communication with micro-
processor
Interrupt generation upon transmission of
message
LOS Insertion enabled by register bit
AIS Insertion enabled by register bit or pin
Idle signal insertion enabled by register bit
Supports B3ZS encoding
Generates AIS, Idle and Yellow force alarms
Inserts errors optionally in the P F, FEBE and M bits
Provides 15-bit PRBS generator
E3 RECEIVE FRAMER
Offers off-line framing algorithm
Complies with standards ITU-T G.751 and G.832
Provides line code violation detection and excess
zero count
LAPD controller complies with ITU Q.921 LAPD
protocol
Provides local loop-back
Supports G.751 and G.832 framing formats
Supports HDB3 line decoding which can be user
enabled. Replaces valid B00V or 000V with 4 zero’s
Synchronizes to incoming frame based upon occur-
rence of two sets of FA1, FA2 with expected sepa-
ration -G.832 or detection of three consecutive
frame alignment signals (FAS) - G.751
Detects Out of Frame (OOF) upon 4 consecutive
invalid frames
Detects Loss of Signal (LOS) upon encountering 32
consecutive 0’s and clears on occurrence of 32 bits
without a string of 4 0s
Detects AIS if 7 or less 0s detected in each of 2
consecutive frames and clears if more than seven
0’s detected in each of 2 consecutive frames
Calculation and comparison of BIP-8 (G.832) or
BIP-4 (G.751). BIP-4 calculation can be disabled
Supports overhead extraction
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT94L33IB | highly integrated SONET/SDH terminator |
| XRT94L55 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT94L55IV | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT95L51IB | STORAGE, SLIDES CABINET RoHS Compliant: Yes |
| XRT95L34 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT94L33_06 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET |
| XRT94L33_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER - ATM REGISTERS |
| XRT94L33_1 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER ATM/PPP - HARWARE MANUAL |
| XRT94L33_2 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER - SDH REGISTERS |
| XRT94L33_3 | 制造商:EXAR 制造商全稱:EXAR 功能描述:-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER - SONET REGISTERS |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。