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參數(shù)資料
| 型號： | XRT94L43IB |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET/SDH STS-12/STM-4 TO E3/DS3/STS-1 MAPPER/DEMAPPER |
| 中文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PBGA516 |
| 封裝： | 35 X 35 MM, PLASTIC, BGA-516 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大小： | 180K |
| 代理商： | XRT94L43IB |
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XRT94L43
SONET/SDH STS-12/STM-4 12 E3/DS3/STS-1 MAPPER
PRELIMINARY
REV. P1.0.0
5
Microprocessor access to TR trail trace message -
16 TTB registers (G.832) or service (Alarm and
Nation) bits (G.751)
Detects MA FERF if 3 or 5 consecutive MA MSBs
are 1and clears if 3 or 5 consecutive MA MSBs are
0 (only E3 G.832)
Indicates last validated FERF value and interrupt
upon a change in validated FERF value
Extracts payload type (MA) bits and stores in a reg-
ister (Only E3 G.832)
Extracts Timing Marker bit and checks for consis-
tency over 3 or 5 consecutive frames (only E3
G.832)
Extracts Synchronous Status Message bits and
stores it in register bits when enabled (only G.832)
Overhead output on synchronous serial interface
E3 TRANSMIT FRAMER
Offers following frame generation mechanism:
Asynchronous operation, using receive side clock,
external framing
Supports either G.751 or G.832 framing format
Generates and checks parity BIP-8 (G.832), BIP-4
(G.751) BIP-4 computation can be disabled
Inserts data link message through E3 data line
channel which contains the following features:
Insertion into NR or GC byte (programmable
through register bit) (E3 G.832 only)
Insertion into Nation bit in case of E3 G.751
when LAPD is enabled
RAM storage of entire LAPD message
Selection of message length to 82 or 76
bytes
Generation of flag sequences
Computation and insertion of CRC-16
Zero stuffing
Register bits for communication with micro-
processor
Interrupt generation upon complete transmis-
sion of message
LOS insertion enabled by register bit to force all 0s
in the transmit stream
AIS insertion enabled by register bit and/or pin to
force all 1’s in the transmit stream
Supports HDB3 encoding enabled by register bit
Inserts frame overhead bits via External serial/nib-
ble port (except for FA1,FA2 and EM bytes in case
of E3 G.832 and FAS and BIP-4 in case of G.751)
or through external overhead interface or from con-
figuration register or internal generation
Inserts FA1, FA2, EM, TR, MA and GC bytes into
G.832 stream or FAS service bits and BIP4 (if
enabled) into G.751 stream
Inserts MA,NR,GC and TR (TTB) from micropro-
cessor accessible registers (service bit for G.751)
Inserts FEBE in MA upon receipt of EM byte errors.
Programmable through register bit (G.832)
Asserts FERF upon any combination of LOS,OOF
or AIS received from receiver (G.832)
Inserts synchronous status message from micro-
processor accessible registers, when enabled
(G.832)
Error masks for framing bytes, and computed parity
(BIP-8 in case of G.832 and BIP-4 in case of
G.751)
Optionally accepts overhead bits (except FA bytes
for G.832 and FAS bits for G.751) from input inter-
face
E3/DS3/STS-1 DE-JITTERING/DE-SYNC CIRCUIT
Meets the E3/DS3/STS-1 jitter requirements
Compliant with jitter transfer template outlined in
ITU G.751,G.752,G.755 and GR-499-CORE
Meets output jitter requirement as specified by
ETSI TBR24
Meets the jitter and wander specifications
described in T1.105.03b,GR-253 and GR-499 stan-
dards
Performs the Desynchronizer function and pointer
adjustments for STS-1 to DS3 mapping
.PERFORMANCE MONITORING
Supports line and path performance monitoring
Provides 32-bit saturating counter of OOF errors
Provides 32-bit saturating counter LOF errors
Provides 32-bit saturating counter of LOS errors
Provides 32-bit saturating counter of SD errors
Provides 32-bit saturating counter of SF errors
Provides 32-bit saturating counter B3 errors
Provides 32-bit saturating counter of the line
RDI,path AIS,REI-L errors,REI-P errors and BIP-
8(B1,B2),B3 errors and loss of pointer
Provides 16-bit saturating counter of DS3 framing
bit errors, DS3 frame parity errors, line code viola-
tions, frame parity (BIP) errors, DS3 frame CP bit
errors and DS3 Far-End Block errors
One second statistics
1. Bipolar violations
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT94L33 | highly integrated SONET/SDH terminator |
| XRT94L33IB | highly integrated SONET/SDH terminator |
| XRT94L55 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT94L55IV | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT95L51IB | STORAGE, SLIDES CABINET RoHS Compliant: Yes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT94L43IB-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Demapper RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT94L55 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SONET/SDH OC-48/STM-16, 4XOC-12/STM-4, 16XOC-3/STM-1 FRAMER/CONCENTRATOR WITH INTEGRATED CDR’S |
| XRT94L55IV | 制造商:EXAR 制造商全稱:EXAR 功能描述:SONET/SDH OC-48/STM-16, 4XOC-12/STM-4, 16XOC-3/STM-1 FRAMER/CONCENTRATOR WITH INTEGRATED CDR’S |
| XRT95L34 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OC-12/STM-4, QUAD OC-3/STM-1 POS/ATM FRAMER WITH INTEGRATED CDR’S |
| XRT95L34IV | 制造商:EXAR 制造商全稱:EXAR 功能描述:OC-12/STM-4, QUAD OC-3/STM-1 POS/ATM FRAMER WITH INTEGRATED CDR’S |
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