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參數(shù)資料
| 型號： | XWM8722EDS |
| 廠商： | Wolfson Microelectronics |
| 英文描述： | Stereo DAC with Integrated Tone Generator and Line/Variable Level Outputs |
| 中文描述： | 立體聲DAC，具有集成的音調(diào)發(fā)生器和線/變平輸出 |
| 文件頁數(shù)： | 19/23頁 |
| 文件大小： | 438K |
| 代理商： | XWM8722EDS |
Advanced Information
WM8722
WOLFSON MICROELECTRONICS LTD
AI Rev 1.5 May 2000
19
BOTH
In register 4 and 5, a further bit BOTH is available: When a write is made to either register 4 or 5 and
BOTH is set high, then the same value written to the register will also be written into the other
register. This allows both Left and Right channel gains to be updated simultaneously, halving the
number of serial writes required, (simplifying gain ramping, for example) provided that the same gain
is needed for both channels.
REGISTER 6/7
VOLUME CONTROL
Bits 0-6 of register 6, LVOL[6:0], control gain applied to the variable level output VAROUTL. This 6-
bit register controls 1.0 dB increments of the volume, over a range of +6 dB to
–
73 dB.
Similarly bits 0-6 of register 7, RVOL[6:0], control the gain applied to the variable level output
VAROUTR. Value 1111111 sets maximum, i.e. 6dB gain. Code 48 sets minimum gain. Values less
than code 48 apply mute to the gain stage. (i.e. set volume to 000 0000 to achieve mute)
ZCEN
A zero cross detect circuit is provided, so that volume control values are only updated when the input
signal to the gain stage is close to the analogue ground level, minimising clicks and zipper noise as
the gain values are changed. This circuit has no time out so if DC levels are being applied to the gain
stage input, then the gain will not be updated. This zero cross function is enabled when the ZCEN bit
is set high during a volume register write. If there is concern that a DC level may have blocked a
volume change (one made with ZCEN set high), then a subsequent volume write of the same value,
but with the ZCEN bit set low will force a volume update regardless of the DC level.
BOTH
In register 6 and 7, a further bit BOTH is available. When a write is made to either register 6 or 7 and
BOTH is set high, then the same value written to the register will also be written into the other
register. This allows both Left and Right channel gains to be updated simultaneously, halving the
number of serial writes required, provided that the same gain is needed for both channels.
REGISTER 8, 9, 10, 11
ANALOGUE MIXER OUTPUT SELECTION
The WM8722 allows software controllable selection of signal outputs. The WM8722 allows 2 outputs
per channel, with one output at line level, and another output at variable level, according to the
LVOL[6:0] and RVOL[6:0] attenuation register settings. In addition, the user may select whether the
left or the right signal, converted in the DAC, is mixed with the corresponding mixer input or not.
This switching scheme is detailed in Figure 9, with 10 different select signals per channel, 5 each for
each Mux: Each Mux therefore has 5 input signals; DACL, DACR, MIXL, MIXR and TONE. This
allows completely flexible selection of signal paths, both mono and stereo outputs, on any output.
MUX CONTROL BITS MXSEL(4:0)
0
1
2
3
4
Table 10. MUX(4:0) mux control switches
SIGNAL SELECTED WHEN HIGH IS SET
DAC sum enable
MIXIN sum enable
TONE in sum enable
Opposite channel DAC sum enable
Opposite channel MIXIN sum enable
If mono outputs are selected, the gain through the summer amplifiers may be reduced by 6dB if
required by setting the appropriate M6DB bits. Similarly left and right channels may be completely
swapped.
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| XWM8733ED | 制造商:WOLFSON 制造商全稱:WOLFSON 功能描述:102dB Stereo DAC |
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