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參數(shù)資料
| 型號： | XWM8740EDS |
| 廠商： | Wolfson Microelectronics |
| 英文描述： | 24-bit, High Performance 192kHz Stereo DAC |
| 中文描述： | 24位高性能192kHz的立體聲DAC |
| 文件頁數(shù)： | 6/20頁 |
| 文件大小： | 344K |
| 代理商： | XWM8740EDS |
WM8740
Advanced Information
WOLFSON MICROELECTRONICS LTD
AI Rev 1.7 July 2000
6
Test Conditions
AVDD, DVDD = 5V, AGND, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
DIN setup time
DIN hold time
SYMBOL
t
DS
t
DH
TEST CONDITIONS
MIN
20
20
TYP
MAX
UNIT
ns
ns
SCKI
t
SCKIL
t
SCKIH
t
SCKY
Figure 2 System Clock Timing Requirements
Test Conditions
AVDD, DVDD = 5V, AGND, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
System Clock Timing Information
System clock pulse width high
System clock pulse width low
System clock cycle time
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
SCKIH
t
SCKIL
t
SCKY
10
10
27
ns
ns
ns
ML/I2S
MC/DM1
MD/DM0
t
MHH
t
MLD
t
MCY
t
MCH
t
MCL
t
MDS
t
MDH
LSB
t
MLS
t
MLL
Figure 3 Program Register Input Timing – SPI Compatible Serial Control Mode
Test Conditions
AVDD, DVDD = 5V, AGND, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
Program Register Input Information
MC/DM1 pulse cycle time
MC/DM1 pulse width low
MD/DM0 pulse width high
MD/DM0 set-up time
MC/DM1 hold time
ML/I2S pulse width low
ML/I2S pulse width high
ML/I2S set-up time
ML/I2S delay from MC
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
MCY
t
MCL
t
MCH
t
MDS
t
MDH
t
MLL
t
MHH
t
MLS
t
MLD
80
32
32
10
10
10
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
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